Hannes Groß

Orcid: 0000-0003-1262-8076

Affiliations:
  • Graz University of Technology, Institute for Applied Information Processing and Communications (IAIK), Austria


According to our database1, Hannes Groß authored at least 24 papers between 2010 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

Online presence:

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Bibliography

2019
Protecting against Statistical Ineffective Fault Attacks.
IACR Cryptol. ePrint Arch., 2019

First-Order Masking with Only Two Random Bits.
Proceedings of ACM Workshop on Theory of Implementation Security, 2019

2018
Generic Low-Latency Masking in Hardware.
IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

A unified masking approach.
J. Cryptogr. Eng., 2018

Masking the AES with Only Two Random Bits.
IACR Cryptol. ePrint Arch., 2018

Sharing Independence & Relabeling: Efficient Formal Verification of Higher-Order Masking.
IACR Cryptol. ePrint Arch., 2018

Formal Verification of Masked Hardware Implementations in the Presence of Glitches.
Proceedings of the Advances in Cryptology - EUROCRYPT 2018 - 37th Annual International Conference on the Theory and Applications of Cryptographic Techniques, Tel Aviv, Israel, April 29, 2018

Statistical Ineffective Fault Attacks on Masked AES with Fault Countermeasures.
Proceedings of the Advances in Cryptology - ASIACRYPT 2018, 2018

2017
Ascon hardware implementations and side-channel evaluation.
Microprocess. Microsystems, 2017

Reconciling d+1Masking in Hardware and Software.
IACR Cryptol. ePrint Arch., 2017

Generic Low-Latency Masking.
IACR Cryptol. ePrint Arch., 2017

Higher-Order Side-Channel Protected Implementations of KECCAK.
Proceedings of the Euromicro Conference on Digital System Design, 2017

An Efficient Side-Channel Protected AES Implementation with Arbitrary Protection Order.
Proceedings of the Topics in Cryptology - CT-RSA 2017, 2017

Reconciling d+1 Masking in Hardware and Software.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2017, 2017

2016
HF/UHF dual band RFID transponders for an information-driven public transportation system.
Elektrotech. Informationstechnik, 2016

Domain-Oriented Masking: Compact Masked Hardware Implementations with Arbitrary Protection Order.
Proceedings of the ACM Workshop on Theory of Implementation Security, 2016

Concealing Secrets in Embedded Processors Designs.
Proceedings of the Smart Card Research and Advanced Applications, 2016

2015
Sharing is Caring - On the Protection of Arithmetic Logic Units against Passive Physical Attacks.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2015

Concept for a security aware automatic fare collection system using HF/UHF dual band RFID transponders.
Proceedings of the 45th European Solid State Device Research Conference, 2015

Suit up! - Made-to-Measure Hardware Implementations of ASCON.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

Privacy-Aware Authentication in the Internet of Things.
Proceedings of the Cryptology and Network Security - 14th International Conference, 2015

2014
PIONEER - a Prototype for the Internet of Things Based on an Extendable EPC Gen2 RFID Tag.
Proceedings of the Radio Frequency Identification: Security and Privacy Issues, 2014

2012
On Using Instruction-Set Extensions for Minimizing the Hardware-Implementation Costs of Symmetric-Key Algorithms on a Low-Resource Microcontroller.
Proceedings of the Radio Frequency Identification. Security and Privacy Issues, 2012

2010
Implementation of Symmetric Algorithms on a Synthesizable 8-Bit Microcontroller Targeting Passive RFID Tags.
Proceedings of the Selected Areas in Cryptography - 17th International Workshop, 2010


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