Roderick Bloem

According to our database1, Roderick Bloem
  • authored at least 103 papers between 1997 and 2017.
  • has a "Dijkstra number"2 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Other 

Links

Homepage:

On csauthors.net:

Bibliography

2017
The first reactive synthesis competition (SYNTCOMP 2014).
STTT, 2017

Shield synthesis.
Formal Methods in System Design, 2017

Safe Reinforcement Learning via Shielding.
CoRR, 2017

Synthesizing Non-Vacuous Systems.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2017

Model-Based Testing IoT Communication via Active Automata Learning.
Proceedings of the 2017 IEEE International Conference on Software Testing, 2017

Bounded Synthesis for Streett, Rabin, and \text CTL^*.
Proceedings of the Computer Aided Verification - 29th International Conference, 2017

Towards a Secure SCRUM Process for Agile Web Application Development.
Proceedings of the 12th International Conference on Availability, Reliability and Security, Reggio Calabria, Italy, August 29, 2017

2016
Decidability in Parameterized Verification.
SIGACT News, 2016

Dependability for the Internet of Things - from dependable networking in harsh environments to a holistic view on dependability.
Elektrotechnik und Informationstechnik, 2016

The 3rd Reactive Synthesis Competition (SYNTCOMP 2016): Benchmarks, Participants & Results.
Proceedings of the Proceedings Fifth Workshop on Synthesis, 2016

The Reactive Synthesis Competition: SYNTCOMP 2016 and Beyond.
Proceedings of the Proceedings Fifth Workshop on Synthesis, 2016

Satisfiability-Based Methods for Reactive Synthesis from Safety Specifications.
CoRR, 2016

QBF Solving by Counterexample-guided Expansion.
CoRR, 2016

Synthesizing adaptive test strategies from temporal logic specifications.
Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.
Proceedings of the 2016 Forum on Specification and Design Languages, 2016

SMT-Based CPS Parameter Synthesis.
Proceedings of the ARCH@CPSWeek 2016, 2016

Synthesis of Self-Stabilising and Byzantine-Resilient Distributed Systems.
Proceedings of the Computer Aided Verification - 28th International Conference, 2016

2015
Decidability of Parameterized Verification
Synthesis Lectures on Distributed Computing Theory, Morgan & Claypool Publishers, 2015

The Second Reactive Synthesis Competition (SYNTCOMP 2015).
Proceedings of the Proceedings Fourth Workshop on Synthesis, 2015

The First Reactive Synthesis Competition (SYNTCOMP 2014).
CoRR, 2015

Shield Synthesis: Runtime Enforcement for Reactive Systems.
CoRR, 2015

Cooperative Reactive Synthesis.
CoRR, 2015

Case Study: Automatic Test Case Generation for a Secure Cache Implementation.
Proceedings of the Tests and Proofs - 9th International Conference, 2015

Shield Synthesis: - Runtime Enforcement for Reactive Systems.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2015

Assume-Guarantee Synthesis for Concurrent Reactive Programs with Partial Information.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2015

Synthesizing cooperative reactive mission plans.
Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015

Reactive Synthesis.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Cooperative Reactive Synthesis.
Proceedings of the Automated Technology for Verification and Analysis, 2015

2014
Automatic Error Localization for Software using Deductive Verification.
CoRR, 2014

Parameterized Synthesis.
Logical Methods in Computer Science, 2014

Parameterized Synthesis Case Study: AMBA AHB.
Proceedings of the Proceedings 3rd Workshop on Synthesis, 2014

Parameterized Synthesis Case Study: AMBA AHB.
CoRR, 2014

SAT-Based Methods for Circuit Synthesis.
CoRR, 2014

How to Handle Assumptions in Synthesis.
Proceedings of the Proceedings 3rd Workshop on Synthesis, 2014

Assume-Guarantee Synthesis for Concurrent Reactive Programs with Partial Information.
CoRR, 2014

Synthesizing robust systems.
Acta Inf., 2014

SAT-Based Synthesis Methods for Safety Specs.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2014

Automating Test-Suite Augmentation.
Proceedings of the 2014 14th International Conference on Quality Software, 2014

Security concepts for a distributed architecture for activity logging and analysis.
Proceedings of the 14th International Conference on Knowledge Management and Data-driven Business, 2014

Automatic Error Localization for Software Using Deductive Verification.
Proceedings of the Hardware and Software: Verification and Testing, 2014

Reduction of Resolution Refutations and Interpolants via Subsumption.
Proceedings of the Hardware and Software: Verification and Testing, 2014

Synthesis of synchronization using uninterpreted functions.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

SAT-based methods for circuit synthesis.
Proceedings of the Formal Methods in Computer-Aided Design, 2014

2013
Debugging formal specifications: a practical approach using model-based diagnosis and counterstrategies.
STTT, 2013

Synthesizing Multiple Boolean Functions using Interpolation on a Single Proof.
CoRR, 2013

SAT-Based Synthesis Methods for Safety Specs.
CoRR, 2013

Towards Efficient Parameterized Synthesis.
Proceedings of the Verification, 2013

Synthesizing multiple boolean functions using interpolation on a single proof.
Proceedings of the Formal Methods in Computer-Aided Design, 2013

PARTY Parameterized Synthesis of Token Rings.
Proceedings of the Computer Aided Verification - 25th International Conference, 2013

2012
Finding and fixing faults.
J. Comput. Syst. Sci., 2012

Synthesis of Reactive(1) designs.
J. Comput. Syst. Sci., 2012

Synthesizing Robust Systems with RATSY
Proceedings of the Proceedings First Workshop on Synthesis, 2012

Secure Embedded Platform with Advanced Process Isolation and Anonymity Capabilities.
Proceedings of the Trust, Privacy and Security in Digital Business, 2012

Parameterized Synthesis.
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012

Repair with On-The-Fly Program Analysis.
Proceedings of the Hardware and Software: Verification and Testing, 2012

FoREnSiC- An Automatic Debugging Environment for C Programs.
Proceedings of the Hardware and Software: Verification and Testing, 2012

2011
Specification-centered robustness.
Proceedings of the Industrial Embedded Systems (SIES), 2011

Controller synthesis for pipelined circuits using uninterpreted functions.
Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Test Case Generation from Mutants Using Model Checking Techniques.
Proceedings of the Fourth IEEE International Conference on Software Testing, 2011

Generalized Reactivity(1) Synthesis without a Monolithic Strategy.
Proceedings of the Hardware and Software: Verification and Testing, 2011

Automated error localization and correction for imperative programs.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010
Guest Editorial.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Fault localization using a model checker.
Softw. Test., Verif. Reliab., 2010

Debugging Unrealizable Specifications with Model-Based Diagnosis.
Proceedings of the Hardware and Software: Verification and Testing, 2010

RATSY - A New Requirements Analysis Tool with Synthesis.
Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

Robustness in the Presence of Liveness.
Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009
Better Quality in Synthesis through Quantitative Objectives
CoRR, 2009

Debugging formal specifications using simple counterstrategies.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Synthesizing robust systems.
Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Better Quality in Synthesis through Quantitative Objectives.
Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008
Automatic Fault Localization for Property Checking.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2008

Debugging Design Errors by Using Unsatisfiable Cores.
Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Formal Analysis of a TPM-Based Secrets Distribution and Storage Scheme.
Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Open Implication.
Proceedings of the Automata, Languages and Programming, 35th International Colloquium, 2008

Using unsatisfiable cores to debug multiple design errors.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
Symbolic Implementation of Alternating Automata.
Int. J. Found. Comput. Sci., 2007

Automated Fault Localization for C Programs.
Electr. Notes Theor. Comput. Sci., 2007

Preface.
Electr. Notes Theor. Comput. Sci., 2007

Specify, Compile, Run: Hardware from PSL.
Electr. Notes Theor. Comput. Sci., 2007

Fault Localization and Correction with QBF.
Proceedings of the Theory and Applications of Satisfiability Testing, 2007

Interactive presentation: Automatic hardware synthesis from specifications: a case study.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Anzu: A Tool for Property Synthesis.
Proceedings of the Computer Aided Verification, 19th International Conference, 2007

RAT: A Tool for the Formal Analysis of Requirements.
Proceedings of the Computer Aided Verification, 19th International Conference, 2007

2006
Compositional SCC Analysis for Language Emptiness.
Formal Methods in System Design, 2006

An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps.
Formal Methods in System Design, 2006

Symbolic Implementation of Alternating Automata.
Proceedings of the Implementation and Application of Automata, 2006

Automatic Fault Localization for Property Checking.
Proceedings of the Hardware and Software, 2006

Optimizations for LTL Synthesis.
Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Formal analysis of hardware requirements.
Proceedings of the 43rd Design Automation Conference, 2006

Repair of Boolean Programs with an Application to C.
Proceedings of the Computer Aided Verification, 18th International Conference, 2006

2005
Formal Verification of Control Software: A Case Study.
Proceedings of the Innovations in Applied Artificial Intelligence, 2005

Finding and Fixing Faults.
Proceedings of the Correct Hardware Design and Verification Methods, 2005

Program Repair as a Game.
Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2002
Analysis of Symbolic SCC Hull Algorithms.
Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

Fair Simulation Minimization.
Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001
Divide and Compose: SCC Refinement for Language Emptiness.
Proceedings of the CONCUR 2001, 2001

2000
A Comparison of Tree Transductions Defined by Monadic Second Order Logic and by Attribute Grammars.
J. Comput. Syst. Sci., 2000

A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles.
Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

An Algorithm for Strongly Connected Component Analysis in n log n Symbolic Steps.
Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

Symbolic guided search for CTL model checking.
Proceedings of the 37th Conference on Design Automation, 2000

Efficient Büchi Automata from LTL Formulae.
Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999
Efficient Decision Procedures for Model Checking of Linear Time Logic Properties.
Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1997
Monadic Second Order Logic and Node Relations on Graphs and Trees.
Proceedings of the Structures in Logic and Computer Science, 1997


  Loading...