Roderick Bloem

Innov. Syst. Softw. Eng., 2022

Power Contracts: Provably Complete Power Leakage Models for Processors.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2022

Threat Repair with Optimization Modulo Theories.

[BibT_eX]

[DOI]

CoRR, 2022

Conformance Testing of Mealy Machines Under Input Restrictions.

[BibT_eX]

[DOI]

Alberto Larrauri

CoRR, 2022

FERPModels: A Certification Framework for Expansion-Based QBF Solving.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, 2022

Automata Learning Meets Shielding.

[BibT_eX]

[DOI]

Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation. Verification Principles, 2022

Reactive Synthesis Modulo Theories using Abstraction Refinement.

[BibT_eX]

[DOI]

Benedikt Maderbacher

Proceedings of the 22nd Formal Methods in Computer-Aided Design, 2022

Industry Paper: Surrogate Models for Testing Analog Designs under Limited Budget - a Bandgap Case Study.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2022

Correct-by-Construction Runtime Enforcement in AI - A Survey.

[BibT_eX]

[DOI]

Proceedings of the Principles of Systems Design, 2022

2021

Vacuity in synthesis.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2021

Two SAT solvers for solving quantified Boolean formulas with an arbitrary number of quantifier alternations.

[BibT_eX]

[DOI]

Nicolas Braud-Santoni

Formal Methods Syst. Des., 2021

Minimization and Synthesis of the Tail inSequential Compositions of Mealy Machines.

[BibT_eX]

[DOI]

Lázaro Alberto Larrauri

CoRR, 2021

Online Shielding for Stochastic Systems.

[BibT_eX]

[DOI]

Proceedings of the NASA Formal Methods - 13th International Symposium, 2021

Learning Mealy Machines with One Timer.

[BibT_eX]

[DOI]

Frits W. Vaandrager

Masoud Ebrahimi

Proceedings of the Language and Automata Theory and Applications, 2021

COCOALMA: A Versatile Masking Verifier.

[BibT_eX]

[DOI]

Vedad Hadzic

Proceedings of the Formal Methods in Computer Aided Design, 2021

TEMPEST - Synthesis Tool for Reactive Systems and Shields in Probabilistic Environments.

[BibT_eX]

[DOI]

Proceedings of the Automated Technology for Verification and Analysis, 2021

Adaptive Shielding under Uncertainty.

[BibT_eX]

[DOI]

Proceedings of the 2021 American Control Conference, 2021

Adaptive Testing for Specification Coverage in CPS Models.

[BibT_eX]

[DOI]

Proceedings of the 7th IFAC Conference on Analysis and Design of Hybrid Systems, 2021

2020

Coco: Co-Design and Co-Verification of Masked Software Implementations on CPUs.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

Safety Synthesis Sans Specification.

[BibT_eX]

[DOI]

CoRR, 2020

Adaptive Testing for Specification Coverage.

[BibT_eX]

[DOI]

CoRR, 2020

It's Time to Play Safe: Shield Synthesis for Timed Systems.

[BibT_eX]

[DOI]

Peter Gjøl Jensen

Bettina Könighofer

Kim Guldstrand Larsen

Florian Lorber

Alexander Palmisano

CoRR, 2020

Preface for the SYNT.

[BibT_eX]

[DOI]

Paulo Tabuada

Acta Informatica, 2020

Placement of Runtime Checks to Counteract Fault Injections.

[BibT_eX]

[DOI]

Benedikt Maderbacher

Anja F. Karl

Proceedings of the Runtime Verification - 20th International Conference, 2020

Shield Synthesis for Reinforcement Learning.

[BibT_eX]

[DOI]

Proceedings of the Leveraging Applications of Formal Methods, Verification and Validation: Verification Principles, 2020

Safe Reinforcement Learning Using Probabilistic Shields (Invited Paper).

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Concurrency Theory, 2020

2019

Synthesizing adaptive test strategies from temporal logic specifications.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2019

Learning a Behavior Model of Hybrid Systems Through Combining Model-Based Testing and Machine Learning (Full Version).

[BibT_eX]

[DOI]

CoRR, 2019

The 5th Reactive Synthesis Competition (SYNTCOMP 2018): Benchmarks, Participants & Results.

[BibT_eX]

[DOI]

CoRR, 2019

Small Faults Grow Up - Verification of Error Masking Robustness in Arithmetically Encoded Programs.

[BibT_eX]

[DOI]

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2019

Learning a Behavior Model of Hybrid Systems Through Combining Model-Based Testing and Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the Testing Software and Systems, 2019

Synthesizing Reactive Systems Using Robustness and Recovery Specifications.

[BibT_eX]

[DOI]

Proceedings of the 2019 Formal Methods in Computer Aided Design, 2019

Run-Time Optimization for Learned Controllers Through Quantitative Games.

[BibT_eX]

[DOI]

Guy Avni

Bettina Könighofer

Stefan Pranger

Proceedings of the Computer Aided Verification - 31st International Conference, 2019

Efficient Information-Flow Verification Under Speculative Execution.

[BibT_eX]

[DOI]

Yakir Vizel

Proceedings of the Automated Technology for Verification and Analysis, 2019

Synthesis of Minimum-Cost Shields for Multi-agent Systems.

[BibT_eX]

[DOI]

Proceedings of the 2019 American Control Conference, 2019

2018

Graph Games and Reactive Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Model Checking., 2018

Generic Low-Latency Masking in Hardware.

[BibT_eX]

[DOI]

Hannes Groß

Rinat Iusupov

IACR Trans. Cryptogr. Hardw. Embed. Syst., 2018

Sharing Independence & Relabeling: Efficient Formal Verification of Higher-Order Masking.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2018

Shielded Decision-Making in MDPs.

[BibT_eX]

[DOI]

CoRR, 2018

Expansion-Based QBF Solving Without Recursion.

[BibT_eX]

[DOI]

Nicolas Braud-Santoni

Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

Automata Learning for Symbolic Execution.

[BibT_eX]

[DOI]

Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

A Counting Semantics for Monitoring LTL Specifications over Finite Traces.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 30th International Conference, 2018

Bounded Synthesis of Register Transducers.

[BibT_eX]

[DOI]

Benedikt Maderbacher

Proceedings of the Automated Technology for Verification and Analysis, 2018

Safe Reinforcement Learning via Shielding.

[BibT_eX]

[DOI]

Proceedings of the Thirty-Second AAAI Conference on Artificial Intelligence, 2018

2017

The first reactive synthesis competition (SYNTCOMP 2014).

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2017

Generic Low-Latency Masking.

[BibT_eX]

[DOI]

Hannes Groß

Rinat Iusupov

IACR Cryptol. ePrint Arch., 2017

Formal Verification of Masked Hardware Implementations in the Presence of Glitches.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2017

Shield synthesis.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2017

OpenSEA: Semi-Formal Methods for Soft Error Analysis.

[BibT_eX]

[DOI]

CoRR, 2017

The 4th Reactive Synthesis Competition (SYNTCOMP 2017): Benchmarks, Participants & Results.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Sixth Workshop on Synthesis, 2017

CTL* synthesis via LTL synthesis.

[BibT_eX]

[DOI]

Sven Schewe

Proceedings of the Proceedings Sixth Workshop on Synthesis, 2017

Synthesizing Non-Vacuous Systems.

[BibT_eX]

[DOI]

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2017

Synthesis of Distributed Algorithms with Parameterized Threshold Guards.

[BibT_eX]

[DOI]

Proceedings of the 21st International Conference on Principles of Distributed Systems, 2017

Model-Based Testing IoT Communication via Active Automata Learning.

[BibT_eX]

[DOI]

Martin Tappler

Proceedings of the 2017 IEEE International Conference on Software Testing, 2017

Bounded Synthesis for Streett, Rabin, and \text CTL^*.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 29th International Conference, 2017

Towards a Secure SCRUM Process for Agile Web Application Development.

[BibT_eX]

[DOI]

Patrik Maier

Zhendong Ma

Proceedings of the 12th International Conference on Availability, Reliability and Security, Reggio Calabria, Italy, August 29, 2017

2016

Decidability in Parameterized Verification.

[BibT_eX]

[DOI]

SIGACT News, 2016

Dependability for the Internet of Things - from dependable networking in harsh environments to a holistic view on dependability.

[BibT_eX]

[DOI]

Elektrotech. Informationstechnik, 2016

The 3rd Reactive Synthesis Competition (SYNTCOMP 2016): Benchmarks, Participants & Results.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Fifth Workshop on Synthesis, 2016

The Reactive Synthesis Competition: SYNTCOMP 2016 and Beyond.

[BibT_eX]

[DOI]

Proceedings of the Proceedings Fifth Workshop on Synthesis, 2016

Satisfiability-Based Methods for Reactive Synthesis from Safety Specifications.

[BibT_eX]

[DOI]

CoRR, 2016

Synthesizing adaptive test strategies from temporal logic specifications.

[BibT_eX]

[DOI]

Proceedings of the 2016 Formal Methods in Computer-Aided Design, 2016

Designing reliable cyber-physical systems overview associated to the special session at FDL'16.

[BibT_eX]

[DOI]

Proceedings of the 2016 Forum on Specification and Design Languages, 2016

SMT-Based CPS Parameter Synthesis.

[BibT_eX]

[DOI]

Proceedings of the ARCH@CPSWeek 2016, 2016

Synthesis of Self-Stabilising and Byzantine-Resilient Distributed Systems.

[BibT_eX]

[DOI]

Nicolas Braud-Santoni

Proceedings of the Computer Aided Verification - 28th International Conference, 2016

2015

Decidability of Parameterized Verification

[BibT_eX]

[DOI]

Synthesis Lectures on Distributed Computing Theory, Morgan & Claypool Publishers, ISBN: 978-3-031-02011-7, 2015

The Second Reactive Synthesis Competition (SYNTCOMP 2015).

[BibT_eX]

[DOI]

Proceedings of the Proceedings Fourth Workshop on Synthesis, 2015

Case Study: Automatic Test Case Generation for a Secure Cache Implementation.

[BibT_eX]

[DOI]

Proceedings of the Tests and Proofs - 9th International Conference, 2015

Shield Synthesis: - Runtime Enforcement for Reactive Systems.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2015

Assume-Guarantee Synthesis for Concurrent Reactive Programs with Partial Information.

[BibT_eX]

[DOI]

Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2015

Synthesizing cooperative reactive mission plans.

[BibT_eX]

[DOI]

Rüdiger Ehlers

Proceedings of the 2015 IEEE/RSJ International Conference on Intelligent Robots and Systems, 2015

Reactive Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2015

Cooperative Reactive Synthesis.

[BibT_eX]

[DOI]

Rüdiger Ehlers

Proceedings of the Automated Technology for Verification and Analysis, 2015

2014

Parameterized Synthesis.

[BibT_eX]

[DOI]

Log. Methods Comput. Sci., 2014

Parameterized Synthesis Case Study: AMBA AHB.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 3rd Workshop on Synthesis, 2014

How to Handle Assumptions in Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 3rd Workshop on Synthesis, 2014

Synthesizing robust systems.

[BibT_eX]

[DOI]

Acta Informatica, 2014

SAT-Based Synthesis Methods for Safety Specs.

[BibT_eX]

[DOI]

Martina Seidl

Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2014

Automating Test-Suite Augmentation.

[BibT_eX]

[DOI]

Proceedings of the 2014 14th International Conference on Quality Software, 2014

Security concepts for a distributed architecture for activity logging and analysis.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Knowledge Management and Data-driven Business, 2014

Automatic Error Localization for Software Using Deductive Verification.

[BibT_eX]

[DOI]

Ronald Toegl

Proceedings of the Hardware and Software: Verification and Testing, 2014

Reduction of Resolution Refutations and Interpolants via Subsumption.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2014

Synthesis of synchronization using uninterpreted functions.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2014

SAT-based methods for circuit synthesis.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2014

2013

Debugging formal specifications: a practical approach using model-based diagnosis and counterstrategies.

[BibT_eX]

[DOI]

Int. J. Softw. Tools Technol. Transf., 2013

Towards Efficient Parameterized Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Verification, 2013

Synthesizing multiple boolean functions using interpolation on a single proof.

[BibT_eX]

[DOI]

Ashutosh Gupta

Bettina Könighofer

Jie-Hong Roland Jiang

Proceedings of the Formal Methods in Computer-Aided Design, 2013

PARTY Parameterized Synthesis of Token Rings.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification - 25th International Conference, 2013

2012

Finding and fixing faults.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 2012

Synthesis of Reactive(1) designs.

[BibT_eX]

[DOI]

J. Comput. Syst. Sci., 2012

Synthesizing Robust Systems with RATSY

[BibT_eX]

[DOI]

Proceedings of the Proceedings First Workshop on Synthesis, 2012

Secure Embedded Platform with Advanced Process Isolation and Anonymity Capabilities.

[BibT_eX]

[DOI]

Marc-Michael Bergfeld

Proceedings of the Trust, Privacy and Security in Digital Business, 2012

Repair with On-The-Fly Program Analysis.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2012

FoREnSiC- An Automatic Debugging Environment for C Programs.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2012

2011

Specification-centered robustness.

[BibT_eX]

[DOI]

Karin Greimel

Proceedings of the Industrial Embedded Systems (SIES), 2011

Controller synthesis for pipelined circuits using uninterpreted functions.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign, 2011

Test Case Generation from Mutants Using Model Checking Techniques.

[BibT_eX]

[DOI]

Heinz Riener

Görschwin Fey

Proceedings of the Fourth IEEE International Conference on Software Testing, 2011

Generalized Reactivity(1) Synthesis without a Monolithic Strategy.

[BibT_eX]

[DOI]

Matthias Schlaipfer

Proceedings of the Hardware and Software: Verification and Testing, 2011

Automated error localization and correction for imperative programs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

2010

Guest Editorial.

[BibT_eX]

[DOI]

Patrick Schaumont

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Fault localization using a model checker.

[BibT_eX]

[DOI]

Softw. Test. Verification Reliab., 2010

Debugging Unrealizable Specifications with Model-Based Diagnosis.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2010

RATSY - A New Requirements Analysis Tool with Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

Robustness in the Presence of Liveness.

[BibT_eX]

[DOI]

Karin Greimel

Proceedings of the Computer Aided Verification, 22nd International Conference, 2010

2009

Debugging formal specifications using simple counterstrategies.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Synthesizing robust systems.

[BibT_eX]

[DOI]

Proceedings of 9th International Conference on Formal Methods in Computer-Aided Design, 2009

Better Quality in Synthesis through Quantitative Objectives.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 21st International Conference, 2009

2008

Automatic Fault Localization for Property Checking.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Debugging Design Errors by Using Unsatisfiable Cores.

[BibT_eX]

Proceedings of the Methoden und Beschreibungssprachen zur Modellierung und Verifikation von Schaltungen und Systemen (MBMV), 2008

Formal Analysis of a TPM-Based Secrets Distribution and Storage Scheme.

[BibT_eX]

[DOI]

Raphael Chung-Wei Phan

Proceedings of the 9th International Conference for Young Computer Scientists, 2008

Open Implication.

[BibT_eX]

[DOI]

Proceedings of the Automata, Languages and Programming, 35th International Colloquium, 2008

Using unsatisfiable cores to debug multiple design errors.

[BibT_eX]

[DOI]

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Symbolic Implementation of Alternating Automata.

[BibT_eX]

[DOI]

Int. J. Found. Comput. Sci., 2007

Specify, Compile, Run: Hardware from PSL.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Compiler Optimization meets Compiler Verification, 2007

Fault Localization and Correction with QBF.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing, 2007

Interactive presentation: Automatic hardware synthesis from specifications: a case study.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Anzu: A Tool for Property Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

RAT: A Tool for the Formal Analysis of Requirements.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 19th International Conference, 2007

2006

Compositional SCC Analysis for Language Emptiness.

[BibT_eX]

[DOI]

Formal Methods Syst. Des., 2006

An Algorithm for Strongly Connected Component Analysis in <i>n</i> log <i>n</i> Symbolic Steps.

[BibT_eX]

[DOI]

Harold N. Gabow

Formal Methods Syst. Des., 2006

Automated Fault Localization for C Programs.

[BibT_eX]

[DOI]

Proceedings of the Workshop on Verification and Debugging, 2006

Preface.

[BibT_eX]

[DOI]

Marco Roveri

Proceedings of the Workshop on Verification and Debugging, 2006

Symbolic Implementation of Alternating Automata.

[BibT_eX]

[DOI]

Proceedings of the Implementation and Application of Automata, 2006

Optimizations for LTL Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 6th International Conference, 2006

Formal analysis of hardware requirements.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

Repair of Boolean Programs with an Application to C.

[BibT_eX]

[DOI]

Byron Cook

Proceedings of the Computer Aided Verification, 18th International Conference, 2006

2005

Formal Verification of Control Software: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the Innovations in Applied Artificial Intelligence, 2005

Finding and Fixing Faults.

[BibT_eX]

[DOI]

Proceedings of the Correct Hardware Design and Verification Methods, 2005

Program Repair as a Game.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 17th International Conference, 2005

2002

Analysis of Symbolic SCC Hull Algorithms.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 4th International Conference, 2002

Fair Simulation Minimization.

[BibT_eX]

[DOI]

Sankar Gurumurthy

Proceedings of the Computer Aided Verification, 14th International Conference, 2002

2001

Divide and Compose: SCC Refinement for Language Emptiness.

[BibT_eX]

[DOI]

Proceedings of the CONCUR 2001, 2001

2000

A Comparison of Tree Transductions Defined by Monadic Second Order Logic and by Attribute Grammars.

[BibT_eX]

[DOI]

Joost Engelfriet

J. Comput. Syst. Sci., 2000

A Comparative Study of Symbolic Algorithms for the Computation of Fair Cycles.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, Third International Conference, 2000

Symbolic guided search for CTL model checking.

[BibT_eX]

[DOI]

Proceedings of the 37th Conference on Design Automation, 2000

Efficient Büchi Automata from LTL Formulae.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 12th International Conference, 2000

1999

Efficient Decision Procedures for Model Checking of Linear Time Logic Properties.

[BibT_eX]

[DOI]

Proceedings of the Computer Aided Verification, 11th International Conference, 1999

1997

Monadic Second Order Logic and Node Relations on Graphs and Trees.

[BibT_eX]

[DOI]