Haoran Pu

Orcid: 0000-0002-6787-5907

According to our database1, Haoran Pu authored at least 9 papers between 2019 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Bibliography

2024
An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs.
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation.
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A CMOS BD-BCI Incorporating Stimulation with Dual-Mode Charge Balancing and Time-Domain Pipelined Recording.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023

2022
A CMOS Dual-Mode Brain-Computer Interface Chipset With 2-mV Precision Time-Based Charge Balancing and Stimulation-Side Artifact Suppression.
IEEE J. Solid State Circuits, 2022

2021
A Fully-Integrated 1µW/Channel Dual-Mode Neural Data Acquisition System for Implantable Brain-Machine Interfaces.
Proceedings of the 43rd Annual International Conference of the IEEE Engineering in Medicine & Biology Society, 2021

A 40V Voltage-Compliance 12.75mA Maximum-Current Multipolar Neural Stimulator Using Time-Based Charge Balancing Technique Achieving 2mV Precision.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2021

2020
An Energy-Efficient CMOS Dual-Mode Array Architecture for High-Density ECoG-Based Brain-Machine Interfaces.
IEEE Trans. Biomed. Circuits Syst., 2020

2019
Study and Design of a Fast Start-Up Crystal Oscillator Using Precise Dithered Injection and Active Inductance.
IEEE J. Solid State Circuits, 2019

Dipole Cancellation as an Artifact Suppression Technique in Simultaneous Electrocorticography Stimulation and Recording.
Proceedings of the 2019 9th International IEEE/EMBS Conference on Neural Engineering (NER), 2019


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