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Mahyar Safiallah

Orcid: 0009-0002-3421-0682

According to our database1, Mahyar Safiallah authored at least 3 papers between 2023 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
An Isolated Frequency Compensation Technique for Ultra-Low-Power Low-Noise Two-Stage OTAs.
[BibTeX]
[DOI]
Ahmad Reza Danesh
,
Mahyar Safiallah
,
Haoran Pu
,
Payam Heydari
IEEE Trans. Circuits Syst. II Express Briefs, January, 2024

2023
A Current-Adjusting Auto-Zeroing Technique for DC-Offset and Flicker-Noise Cancellation.
[BibTeX]
[DOI]
Mahyar Safiallah
,
Ahmad Reza Danesh
,
Haoran Pu
,
Payam Heydari
IEEE Trans. Very Large Scale Integr. Syst., December, 2023

A CMOS BD-BCI Incorporating Stimulation with Dual-Mode Charge Balancing and Time-Domain Pipelined Recording.
[BibTeX]
[DOI]
Haoran Pu
,
Ahmad Reza Danesh
,
Mahyar Safiallah
,
Jeffrey Lim
,
An H. Do
,
Zoran Nenadic
,
Payam Heydari
Proceedings of the IEEE Custom Integrated Circuits Conference, 2023


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