Hau T. Ngo

According to our database1, Hau T. Ngo authored at least 44 papers between 2003 and 2022.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Links

On csauthors.net:

Bibliography

2022
Toward Thermal Imaging Analysis to Characterize Operations of Solid-State Drives via the Temperature Side-Channel.
Proceedings of the 56th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2022, Pacific Grove, CA, USA, October 31, 2022

2021
Detecting firmware modification on solid state drives via current draw analysis.
Comput. Secur., 2021

2020
Classifying Proprietary Firmware on a Solid State Drive Using Idle State Current Draw Measurements.
IEEE Access, 2020

HARDY: Hardware based Analysis for malwaRe Detection in embedded sYstems.
Proceedings of the 33rd IEEE International System-on-Chip Conference, 2020

Efficient architecture design for the AES-128 algorithm on embedded systems.
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020

2019
Monitoring Device Current to Characterize Trim Operations of Solid-State Drives.
IEEE Trans. Inf. Forensics Secur., 2019

Hardware Efficient NIPALS Architecture for Principal Component Analysis of Hyper Spectral Images.
Proceedings of the 32nd IEEE International System-on-Chip Conference, 2019

Using Current Draw Analysis to Identify Suspicious Firmware Behavior in Solid State Drives.
Proceedings of the 2019 IEEE International Conference on Computational Science and Engineering, 2019

2018
Towards detection of modified firmware on solid state drives via side channel analysis.
Proceedings of the International Symposium on Memory Systems, 2018

Classifying Solid State Drive Firmware via Side-Channel Current Draw Analysis.
Proceedings of the 2018 IEEE 16th Intl Conf on Dependable, 2018

2017
Face detection with a Viola-Jones based hybrid network.
IET Biom., 2017

2016
An In Situ Measurement System for Characterizing Orbital Debris.
IEEE Trans. Instrum. Meas., 2016

Use of synthetic data to test biometric algorithms.
J. Electronic Imaging, 2016

Energy Efficient Iris Recognition With Graphics Processing Units.
IEEE Access, 2016

Inferring read and write operations of solid-state drives based on energy consumption.
Proceedings of the 7th IEEE Annual Ubiquitous Computing, 2016

Inferring trimming activity of solid-state drives based on energy consumption.
Proceedings of the IEEE International Instrumentation and Measurement Technology Conference, 2016

2015
Iris unwrapping using the Bresenham circle algorithm for real-time iris recognition.
Proceedings of the Real-Time Image and Video Processing 2015, 2015

2014
Resource-aware architecture design and implementation of hough transform for a real-time iris boundary detection system.
IEEE Trans. Consumer Electron., 2014

A Viola-Jones based hybrid face detection framework.
Proceedings of the Intelligent Robots and Computer Vision XXXI: Algorithms and Techniques, 2014

2013
Real-time video surveillance on an embedded, programmable platform.
Microprocess. Microsystems, 2013

2012
Real Time Iris Segmentation on FPGA.
Proceedings of the 23rd IEEE International Conference on Application-Specific Systems, 2012

2011
Evaluating the information content of near-infrared iris imagery.
Proceedings of the 4th International Symposium on Applied Sciences in Biomedical and Communication Technologies, 2011

2010
Comparing an FPGA to a Cell for an Image Processing Application.
EURASIP J. Adv. Signal Process., 2010

2009
Partitioning and gating technique for low-power multiplication in video processing applications.
Microelectron. J., 2009

Design of a high performance architecture for real-time enhancement of video stream captured in extremely low lighting environment.
Microprocess. Microsystems, 2009

Design of a Logarithmic Domain 2-D Convolver for Low Power Video Processing Applications.
Proceedings of the Sixth International Conference on Information Technology: New Generations, 2009

A Neighborhood Dependent Approach (NDA) for a Power-Aware Design of a Real-Time Video Enhancement System.
Proceedings of the ISCA 24th International Conference on Computers and Their Applications, 2009

2008
Design of a systolic-pipelined architecture for real-time enhancement of color video stream based on an illuminance-reflectance model.
Integr., 2008

2007
Multiplier-less VLSI architecture for real-time computation of multi-dimensional convolution.
Microprocess. Microsystems, 2007

Design of a Low Power Multiply-Accumulator for 2D Convolution in Video Processing Applications.
Proceedings of the Fourth International Conference on Information Technology: New Generations (ITNG 2007), 2007

Design and Implementation of an Efficient and Power-Aware Architecture for Skin Segmentation in Color Video Stream.
Proceedings of the IEEE International Conference on Application-Specific Systems, 2007

2006
Multi-lane architecture for eigenface based real-time face recognition.
Microprocess. Microsystems, 2006

2005
A pipelined architecture for real-time correction of barrel distortion in wide-angle camera images.
IEEE Trans. Circuits Syst. Video Technol., 2005

An Efficient VLSI Architecture for 2-D Convolution with Quadrant Symmetric Kernels.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Flexible and Efficient Hardware Architecture for Real-Time Face Recognition Based on Eigenface.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Design of a Real Time System for Nonlinear Enhancement of Video Streams by an Integrated Neighborhood Dependent Approach.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

A Visibility Improvement System for Low Vision Drivers by Nonlinear Enhancement of Fused Visible and Infrared Video.
Proceedings of the IEEE Conference on Computer Vision and Pattern Recognition, 2005

A Multi-sensor Image Fusion and Enhancement System for Assisting Drivers in Poor Lighting Conditions.
Proceedings of the 34th Applied Image Pattern Recognition Workshop (AIPR 2005), 2005

Design of an Efficient Multiplier-Less Architecture for Multi-dimensional Convolution.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2004
Design of an Efficient Architecture for Real-time Image Enhancement Based on a Luma-Dependent Nonlinear Approach.
Proceedings of the International Conference on Information Technology: Coding and Computing (ITCC'04), 2004

A Nonlinear Technique for Enhancement of Color Images: An Architectural Perspective for Real-Time Applications.
Proceedings of the 33rd Applied Image Pattern Recognition Workshop (AIPR 2004), 2004

2003
Systolic implementation of 2D block-based Hopfield neural network for efficient pattern association.
Microprocess. Microsystems, 2003

Systolic Array Implementation of Block Based Hopfield Neural Network for Pattern Association.
Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

A Fully Pipelined Architecture for Barrel-Distortion Correction Based on Back Mapping, Linear Interpolation.
Proceedings of the International Conference on Embedded Systems and Applications, 2003


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