Hayato Mashiko

According to our database, Hayato Mashiko authored at least 4 papers between 2014 and 2019.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of five.

2019

Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning.

Kota Muroi, Hayato Mashiko, Yukihide Kohira

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

2016

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework.

Junki Kawaguchi, Hayato Mashiko, Yukihide Kohira

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Yield and power improvement method by post-silicon delay tuning and technology mapping.

Hayato Mashiko, Yukihide Kohira

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2014

A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement.

Hayato Mashiko, Yukihide Kohira

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014