Yukihide Kohira

According to our database, Yukihide Kohira authored at least 33 papers between 2005 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

Visualizing Maps of Visitors' Interest for Museum Exhibits with Single-Board Computers.

Shigeo Takahashi, Yohei Nishidate, Yukihide Kohira, Rentaro Yoshioka

Proceedings of the 27th International Conference Information Visualisation, 2023

Precise Detection of Changes in Relatively Static Environments for Single-Board Computers.

Yohei Nishidate, Yukihide Kohira, Shigeo Takahashi, Rentaro Yoshioka

Proceedings of the 14th IIAI International Congress on Advanced Applied Informatics, 2023

2022

Energy Reduction Methods for Wild Animal Detection Devices.

Reon Sato, Hiroshi Saito, Yoichi Tomioka, Yukihide Kohira

IEEE Access, 2022

2021

Foreword.

Yukihide Kohira

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2021

Design of a Knowledge Experience Based Environment for Museum Data Exploration and Knowledge Creation.

Takayuki Hoshino, Rentaro Yoshioka, Yukihide Kohira

Proceedings of the 14th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2021

Area-efficient Binary and Ternary CNN Accelerator using Random-forest-based Approximation.

Kaisei Kimura, Sho Yatabe, Sora Isobe, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira, Qiangfu Zhao

Proceedings of the Ninth International Symposium on Computing and Networking, 2021

A CNN Approximation Method Based on Low-bit Quantization and Random Forests.

Sho Yatabe, Sora Isobe, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira, Qiangfu Zhao

Proceedings of the 5th IEEE International Conference on Cybernetics, 2021

2020

Battery-Powered Wild Animal Detection Nodes with Deep Learning.

Hiroshi Saito, Tatsuki Otake, Hayato Kato, Masayuki Tokutake, Shogo Semba, Yoichi Tomioka, Yukihide Kohira

IEICE Trans. Commun., 2020

Reliable and Efficient Bear-presence Detection based on Region Proposal of Low-resolution.

Masayuki Tokutake, Kaisei Shimura, Yoichi Tomioka, Hiroshi Saito, Yukihide Kohira

Proceedings of the 2020 IEEE International Conference on Systems, Man, and Cybernetics, 2020

2019

Clustering Method for Reduction of Area and Power Consumption on Post-Silicon Delay Tuning.

Kota Muroi, Hayato Mashiko, Yukihide Kohira

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2019

2016

Technology Mapping Method Using Integer Linear Programming for Low Power Consumption and High Performance in General-Synchronous Framework.

Junki Kawaguchi, Hayato Mashiko, Yukihide Kohira

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2016

Yield and power improvement method by post-silicon delay tuning and technology mapping.

Hayato Mashiko, Yukihide Kohira

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

Manufacturability-aware mask assignment in multiple patterning lithography.

Yukihide Kohira, Atsushi Takahashi, Tomomi Matsui, Chikaaki Kodama, Shigeki Nojima, Satoshi Tanaka

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Fast mask assignment using positive semidefinite relaxation in LELECUT triple patterning lithography.

Yukihide Kohira, Tomomi Matsui, Yoko Yokoyama, Chikaaki Kodama, Atsushi Takahashi, Shigeki Nojima, Satoshi Tanaka

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

A Tuning Method of Programmable Delay Element with an Ordered Finite Set of Delays for Yield Improvement.

Hayato Mashiko, Yukihide Kohira

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

2-SAT Based Linear Time Optimum Two-Domain Clock Skew Scheduling in General-Synchronous Framework.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2014

An Acceleration for Any-Angle Routing Using Quasi-Newton Method on GPGPU.

Takahiro Honda, Yukihide Kohira

Proceedings of the IEEE 8th International Symposium on Embedded Multicore/Manycore SoCs, 2014

Positive Semidefinite Relaxation and Approximation Algorithm for Triple Patterning Lithography.

Tomomi Matsui, Yukihide Kohira, Chikaaki Kodama, Atsushi Takahashi

Proceedings of the Algorithms and Computation - 25th International Symposium, 2014

2-SAT based linear time optimum two-domain clock skew scheduling.

Yukihide Kohira, Atsushi Takahashi

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

An Effective Overlap Removable Objective for Analytical Placement.

Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2013

An acceleration method by GPGPU for analytical placement using quasi-Newton method.

Syota Kuwabara, Yukihide Kohira, Yasuhiro Takashima

Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012

An any-angle routing method using quasi-Newton method.

Yukihide Kohira, Atsushi Takahashi

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

Single-Layer Trunk Routing Using Minimal 45-Degree Lines.

Kyosuke Shinoda, Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

2010

CAFE Router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

2009

MILP-Based Efficient Routing Method with Restricted Route Structure for 2-Layer Ball Grid Array Packages.

Yoichi Tomioka, Yoshiaki Kurata, Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Minimization of Delay Insertion in Clock Period Improvement in General-Synchronous Framework.

Yukihide Kohira, Shuhei Tani, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

A Fast Longer Path Algorithm for Routing Grid with Obstacles Using Biconnectivity Based Length Upper Bound.

Yukihide Kohira, Suguru Suehiro, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

2008

A Fast Clock Scheduling for Peak Power Reduction in LSI.

Yosuke Takahashi, Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A Fast Gate-Level Register Relocation Method for Circuit Size Reduction in General-Synchronous Framework.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

2007

Gate-Level Register Relocation in Generalized Synchronous Framework for Clock Period Minimization.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous Framework.

Yukihide Kohira, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

2006

Evaluation of 3D-packing representations for scheduling of dynamically reconfigurable systems.

Yukihide Kohira, Chikaaki Kodama, Kunihiro Fujiyoshi, Atsushi Takahashi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2005

Clock Period Minimization Method of Semi-Synchronous Circuits by Delay Insertion.

Yukihide Kohira, Atsushi Takahashi

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005