Hayder Mrabet

According to our database, Hayder Mrabet authored at least 15 papers between 2005 and 2009.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2009

Design and Optimization of Reconfigurable Architectures: The FPGA Family. (Conception et optimisation d'architectures reconfigurables de type FPGA).

Hayder Mrabet

PhD thesis, 2009

FPGA Interconnect Topologies Exploration.

Zied Marrakchi, Hayder Mrabet, Umer Farooq, Habib Mehrez

Int. J. Reconfigurable Comput., 2009

Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.

Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez

Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA.

Emna Amouri, Hayder Mrabet, Zied Marrakchi, Habib Mehrez

Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008

The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture.

Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez

Proceedings of the ReConFig'08: 2008 International Conference on Reconfigurable Computing and FPGAs, 2008

Efficient tree topology for FPGA interconnect network.

Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez

Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007

Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances.

Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Efficient Mesh of Tree Interconnect for FPGA Architecture.

Zied Marrakchi, Hayder Mrabet, Christian Masson, Habib Mehrez

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

2006

Performance Improvement of FPGA Using Novel Multilevel Hierarchical Interconnection Structure.

Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez, André Tissot

Proceedings of the 2nd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2006

A new Multilevel Hierarchical MFPGA and its suitable configuration tools.

Zied Marrakchi, Hayder Mrabet, Habib Mehrez

Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006

Performances improvement of FPGA using novel multilevel hierarchical interconnection structure.

Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

Configuration tools for a new multilevel hierarchical FPGA.

Zied Marrakchi, Hayder Mrabet, Habib Mehrez

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A multilevel hierarchical interconnection structure for FPGA.

Hayder Mrabet, Zied Marrakchi, Pierre Souillot, Habib Mehrez

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005

Implementation of Scalable Embedded FPGA for SOC.

Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot

Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2005

Hierarchical FPGA clustering based on multilevel partitioning approach to improve routability and reduce power dissipation.

Zied Marrakchi, Hayder Mrabet, Habib Mehrez

Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005