Emna Amouri

Orcid: 0000-0003-2107-3658

According to our database1, Emna Amouri authored at least 24 papers between 2008 and 2017.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Bibliography

2017
Performance analysis and optimization of cluster-based mesh FPGA architectures: design methodology and CAD tool support.
Turkish J. Electr. Eng. Comput. Sci., 2017

On Exploiting Partitioning-Based Placement Approach for Performances Improvement of 3D FPGA.
Proceedings of the 2017 International Conference on High Performance Computing & Simulation, 2017

2016
Improvement of cluster-based Mesh FPGA architecture using novel hierarchical interconnect topology and long routing wires.
Microprocess. Microsystems, 2016

Exploration of Mesh-Based FPGA Architecture: Comparison of 2D and 3D Technologies in Terms of Power, Area and Performance.
Proceedings of the 24th Euromicro International Conference on Parallel, 2016

The effect of interconnect depopulation on FPGA performances in terms of power, area and delay.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Design of advanced 2D and 3D FPGAs: Architecture-level exploration and algorithm-level optimization.
Proceedings of the 11th International Design & Test Symposium, 2016

2015
Countering early propagation and routing imbalance of DPL designs in a tree-based FPGA.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

Mesh of Clusters FPGA Architectures: Exploration Methodology and Interconnect Optimization.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015

2014
Architecture level optimization of 3-dimensional tree-based FPGA.
Microelectron. J., 2014

Impact of defect tolerance techniques on the criticality of a SRAM-based mesh of cluster FPGA.
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014

Impact of Cluster Size on Routability, Testability and Robustness of a Cluster in a Mesh FPGA.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Improve defect tolerance in a cluster of a SRAM-based Mesh of Cluster FPGA using hardware redundancy.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Balancing WDDL dual-rail logic in a tree-based FPGA to enhance physical security.
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Three-dimensional Mesh of Clusters: An alternative unified high performance interconnect architecture for 3D-FPGA implementation.
Proceedings of the 2014 International 3D Systems Integration Conference, 2014

2013
Impact of Dual Placement and Routing on WDDL Netlist Security in FPGA.
Int. J. Reconfigurable Comput., 2013

Efficient multilevel interconnect topology for cluster-based mesh FPGA architecture.
Proceedings of the 2012 International Conference on Reconfigurable Computing and FPGAs, 2013

Physical design exploration of 3D tree-based FPGA architecture.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A defect-tolerant cluster in a mesh SRAM-based FPGA.
Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Performance Analysis and Optimization of High Density Tree-Based 3D Multilevel FPGA.
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2013

2011
Differential pair routing to balance dual signals of WDDL designs in cluster-based Mesh FPGA.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

2010
Controlled placement and routing techniques to improve timing balance of WDDL designs in Mesh-based FPGA.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Improving the Security of Dual Rail Logic in FPGA Using Controlled Placement and Routing.
Proceedings of the ReConFig'09: 2009 International Conference on Reconfigurable Computing and FPGAs, 2009

Placement and routing techniques to improve delay balance of WDDL netlist in MFPGA.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

2008
Efficient tree topology for FPGA interconnect network.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008


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