Heejae Hwang

According to our database¹, Heejae Hwang authored at least 2 papers in 2019.

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2019

A 0.8-3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2019

A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization.

[BibT_eX]

[DOI]

Proceedings of the 2019 International SoC Design Conference, 2019