Jongsun Kim

Orcid: 0000-0002-9611-0268

According to our database1, Jongsun Kim authored at least 42 papers between 2002 and 2023.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2023
A GaN Driver IC With a TDC-Based Dead-Time Controller For GaN DC-DC Buck Converters.
Proceedings of the 20th International SoC Design Conference, 2023

2022
A Fast-Lock All-Digital Clock Generator for Energy Efficient Chiplet-Based Systems.
IEEE Access, 2022

A Fast Lock All-Digital Programmable N/M-ratio MDLL Frequency Multiplier Using a Variable Resolution TDC.
Proceedings of the International Conference on Electronics, Information, and Communication, 2022

2021
A 7.68 GHz Fast-Lock Low-Jitter Digital MDLL.
Proceedings of the 18th International SoC Design Conference, 2021

A 0.8-3.5 GHz Shared TDC-Based Fast-Lock All-Digital DLL with a Built-in DCC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020
A low-jitter 2.4 GHz all-digital MDLL with a dithering jitter reduction scheme for 256 times frequency multiplication.
IEICE Electron. Express, 2020

A 7-GHz Fast-Lock Two-Step Time-to-Digital Converter-Based All-Digital DLL.
Circuits Syst. Signal Process., 2020

Development of Artificial Neural Network System to Recommend Process Conditions of Injection Molding for Various Geometries.
Adv. Intell. Syst., 2020

An All-Digital MDLL for Programmable N/M-ratio Frequency Multiplication.
Proceedings of the International SoC Design Conference, 2020

2019
A 0.8-3.4 GHz process variation insensitive duty-cycle corrector for high-speed memory I/O links.
IEICE Electron. Express, 2019

A Low-Power 20 Gbps Multi-phase MDLL-based Digital CDR with Receiver Equalization.
Proceedings of the 2019 International SoC Design Conference, 2019

2018
A Fast-Locking All-Digital Multiplying DLL for Fractional-Ratio Dynamic Frequency Scaling.
IEEE Trans. Circuits Syst. II Express Briefs, 2018

A low-power fast-lock DCC with a digital duty-cycle adjuster for LPDDR3 and LPDDR4 DRAMs.
IEICE Electron. Express, 2018

An anti-harmonic MDLL for phase-aligned on-chip clock multiplication.
IEICE Electron. Express, 2018

A 7-GHz Fast-Lock 2-Step TDC-based All-Digital DLL for Post-DDR4 SDRAMs.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2017
A fast-locking harmonic-free digital DLL for DDR3 and DDR4 SDRAMs.
IEICE Electron. Express, 2017

A 2-4 GHz fast-locking frequency multiplying delay-locked loop.
IEICE Electron. Express, 2017

A 0.15 to 2.2 GHz all-digital delay-locked loop.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A low-power SerDes for high-speed on-chip networks.
Proceedings of the International SoC Design Conference, 2017

2016
A MDLL-based multi-phase clock multiplier.
Proceedings of the International SoC Design Conference, 2016

A fast-locking clock multiplying DLL.
Proceedings of the International SoC Design Conference, 2016

2012
An Energy-Efficient and High-Speed Mobile Memory I/O Interface Using Simultaneous Bi-Directional Dual (Base+RF)-Band Signaling.
IEEE J. Solid State Circuits, 2012

A programmable delay-locked loop based clock multiplier.
Proceedings of the International SoC Design Conference, 2012

Double edge trailing PWM based full digital audio amplifier design.
Proceedings of the IEEE International Conference on Consumer Electronics, 2012

2011
A Low-Overhead and Low-Power RF Transceiver for Short-Distance On- and Off-Chip Interconnects.
IEICE Trans. Electron., 2011

An 8.4Gb/s 2.5pJ/b mobile memory I/O interface using simultaneous bidirectional Dual (Base+RF) band signaling.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2010
A low-power wideband multi-frequency synthesizer for mobile TV tuner ICs.
IEICE Electron. Express, 2010

2009
Area-efficient digitally controlled CMOS feedback delay element with programmable duty cycle.
IEICE Electron. Express, 2009

2008
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems.
IEEE Trans. Computers, 2008

2007
Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Changeable Face Representations Suitable for Human Recognition.
Proceedings of the Advances in Biometrics, International Conference, 2007

A Changeable Biometric System That Uses Parts-Based Localized Representation for Face Recognition.
Proceedings of the 2007 IEEE Workshop on Automatic Identification Advanced Technologies, 2007

2005
Effective Representation Using ICA for Face Recognition Robust to Local Distortion and Partial Occlusion.
IEEE Trans. Pattern Anal. Mach. Intell., 2005

A 5.6-mW 1-Gb/s/pair pulsed signaling transceiver for a fully AC coupled bus.
IEEE J. Solid State Circuits, 2005

Robust Face Recognition Based on Part-Based Localized Basis Images.
Proceedings of the Image Analysis and Processing, 2005

2004
ICA Based Face Recognition Robust to Partial Occlusions and Local Distortions.
Proceedings of the Biometric Authentication, First International Conference, 2004

Face Recognition Based on Locally Salient ICA Information.
Proceedings of the Biometric Authentication, 2004

A low power capacitive coupled bus interface based on pulsed signaling.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Robust Skin Color Segmentation Using a 2D Plane of RGB Color Space.
Proceedings of the Computer and Information Sciences, 2003

Reconfigurable memory bus systems using multi-Gbps/pin CDMA I/O transceivers.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A 2-Gb/s/pin source synchronous CDMA bus interface with simultaneous multi-chip access and reconfigurable I/O capability.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003

2002
Face Recognition Based on ICA Combined with FLD.
Proceedings of the Biometric Authentication, 2002


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