Hiroaki Ishihara

According to our database1, Hiroaki Ishihara authored at least 9 papers between 2005 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2020
18.7 A DC to 35MHz Fully Integrated Single-Power-Supply Isolation Amplifier for Current- and Voltage-Sensing Front-Ends of Power Electronics.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

18.8 A Fully-Generic-Process Galvanic Isolator for Gate Driver with 123mW 23% Power Transfer and Full-Triplex 21/14/0.5Mb/s Bidirectional Communication Utilizing Reference-Free Dual-Modulation FSK.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2012
A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion.
IEEE J. Solid State Circuits, 2012

2011
A 130μA wake-up receiver SoC in 0.13μm CMOS for reducing standby power of an electric appliance controlled by an infrared remote controller.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 1.9/2.4GHz dual band CMOS power amplifier with integrated AM-PM distortion canceller.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

2010
A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization.
IEEE J. Solid State Circuits, 2010

A 10MHz signal bandwidth Cartesian-loop transmitter capable of off-chip PA linearization.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2008
0.13 μm CMOS Cartesian loop transmitter IC with fast calibration and switching scheme from opened to closed loop.
Proceedings of the ESSCIRC 2008, 2008

2005
A widely tunable Gm-C filter using tail current offset in two differential pairs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005


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