Toshimasa Matsuoka

Orcid: 0000-0003-3876-2679

According to our database1, Toshimasa Matsuoka authored at least 52 papers between 2001 and 2019.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

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Bibliography

2019
A Software Level Calibration Based on Bayesian Regression for a Successive Stochastic Approximation Analog-to-Digital Converter System.
IEEE Trans. Cybern., 2019

A Biomedical Sensor System With Stochastic A/D Conversion and Error Correction by Machine Learning.
IEEE Access, 2019

2017
Behavior-Level Analysis of a Successive Stochastic Approximation Analog-to-Digital Conversion System for Multi-Channel Biomedical Data Acquisition.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2017

An analog front-end employing 87 dB SNDR stochastic SAR-ADC for a biomedical sensor.
Proceedings of the 15th IEEE International New Circuits and Systems Conference, 2017

A calibration with an adaptive data selection based on Bayes estimation for a successive stochastic approximation ADC system.
Proceedings of the Joint 17th World Congress of International Fuzzy Systems Association and 9th International Conference on Soft Computing and Intelligent Systems, 2017

2016
A Design of 0.7-V 400-MHz All-Digital Phase-Locked Loop for Implantable Biomedical Devices.
IEICE Trans. Electron., 2016

An offset distribution modification technique of stochastic flash ADC.
IEICE Electron. Express, 2016

2015
RF front-end architecture for a triple-band CMOS GPS receiver.
Microelectron. J., 2015

A Delta-Sigma ADC with Stochastic Quantization.
IPSJ Trans. Syst. LSI Des. Methodol., 2015

A Design of 0.7-V 400-MHz Digitally-Controlled Oscillator.
IEICE Trans. Electron., 2015

A low-power CMOS programmable frequency divider with novel retiming scheme.
IEICE Electron. Express, 2015

A low-voltage design of controller-based ADPLL for implantable biomedical devices.
Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

2014
Extra loop delay compensation for hybrid delta-sigma modulators.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A low-power technique for pipelined ADCs with programmable gain amplification.
IEICE Electron. Express, 2013

Low-power wireless on-chip microparticle manipulation with process variation compensation.
IEICE Electron. Express, 2013

Design of triple-band CMOS GPS receiver RF front-end.
IEICE Electron. Express, 2013

2012
Wireless on-chip microparticle manipulation using pulse-driven dielectrophoresis.
IEICE Electron. Express, 2012

A novel RC time constant tuning technique utilizing programmable current sources for continuous-time delta-sigma modulators.
IEICE Electron. Express, 2012

2011
Low-power zero-IF full-segment ISDB-T CMOS tuner with tenth-order baseband filters.
IEEE Trans. Consumer Electron., 2011

A Wide Dynamic Range Variable Gain Amplifier with Enhanced IP1 dB and Temperature Compensation.
IEICE Trans. Electron., 2011

Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process.
IEICE Electron. Express, 2011

2010
Rf front-end design for CMOS terrestrial wideband TV tuner IC.
IEEE Trans. Consumer Electron., 2010

Low-Voltage Wireless Analog CMOS Circuits toward 0.5 V Operation.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

A Transformer Noise-Canceling Ultra-Wideband CMOS Low-Noise Amplifier.
IEICE Trans. Electron., 2010

Design of a low-voltage CMOS mixer based on variable load technique.
IEICE Electron. Express, 2010

2009
A 0.5 V Area-Efficient Transformer Folded-Cascode CMOS Low-Noise Amplifier.
IEICE Trans. Electron., 2009

Application of Noise-Enhanced Detection of Subthreshold Signals for Communication Systems.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Analytical design of a 0.5V 5GHz CMOS LC-VCO.
IEICE Electron. Express, 2009

A 0.5 V feedforward delta-sigma modulator with inverter-based integrator.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Design of a 0.5 V Op-Amp Based on CMOS Inverter Using Floating Voltage Sources.
IEICE Trans. Electron., 2008

A novel approach to implement summing function for feedforward Δ-Σ AD modulator.
IEICE Electron. Express, 2008

Sub-threshold signal detection using noise statistics for communications applications.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

2007
Analytical Expression Based Design of a Low-Voltage FD-SOI CMOS Low-Noise Amplifier.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007

2006
Accurate Small-Signal Modeling of FD-SOI MOSFETs.
IEICE Trans. Electron., 2006

Analytical GMD formulas for mutual inductance calculation of multilevel interconnects.
IEICE Electron. Express, 2006

2005
CMOS Front-End Circuits of Dual-Band GPS Receiver.
IEICE Trans. Electron., 2005

A New Inductance Extraction Technique of On-Wafer Spiral Inductor Based on Analytical Interconnect Formula.
IEICE Trans. Electron., 2005

Wired CDMA Interface with Adaptivity for Interconnect Capacitances.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Ultralow-Power Current Reference Circuit with Low Temperature Dependence.
IEICE Trans. Electron., 2005

A CMOS IF Variable Gain Amplifier with Exponential Gain Control.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Experimental study of integrated tunable transformer.
IEICE Electron. Express, 2005

A 1-V 120-MHz FD-SOI CMOS linear-in-dB variable gain amplifier.
IEICE Electron. Express, 2005

A widely tunable Gm-C filter using tail current offset in two differential pairs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Drain current response delay of FD-SOI MOSFETs in RF operation.
IEICE Electron. Express, 2004

A dual-band image-reject mixer for GPS with 64dB image rejection.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
A New Analog Correlator Circuit for DS-CDMA Wireless Applications.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

Parallel bus systems using code-division multiple access technique.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Multiple-bit parallel-CDMA technique for an on-chip interface featuring high data transmission rate, small latency and high noise tolerance.
Proceedings of the ESSCIRC 2003, 2003

2002
A study of robustness and coupling-noise immunity on simultaneous data transfer CDMA bus interface.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

CMOS phase-shift VCO for short-range wireless communication.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

2001
A novel dynamically programmable arithmetic array using code division multiple access bus.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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