Hiroyuki Miyakawa

According to our database, Hiroyuki Miyakawa authored at least 3 papers between 1991 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2003

Scalable Parasitic Components Model of CMOS for RF Circuit Design.

Nobuyuki Itoh, Tatsuya Ohguro, Kazuhiro Katoh, Hideki Kimijima, Shin-ichiro Ishizuka, Kenji Kojima, Hiroyuki Miyakawa

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

1992

0.5- mu m 3.3-V BiCMOS standard cells with 32-kilobyte cache and ten-port register file.

Hiroyuki Hara, Takayasu Sakurai, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Kouji Matsuda, Yoshinori Watanabe, Fumihiko Sano, Akihiko Chiba

IEEE J. Solid State Circuits, November, 1992

1991

0.5- mu m 2 M-transistor BiPNMOS channelless gate array.

Hiroyuki Hara, Takayasu Sakurai, Makoto Noda, Tetsu Nagamatsu, Katsuhiro Seta, Hiroshi Momose, Yoichirou Niitsu, Hiroyuki Miyakawa, Yoshinori Watanabe

IEEE J. Solid State Circuits, November, 1991