Fumihiko Sano

According to our database, Fumihiko Sano authored at least 8 papers between 1996 and 2003.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2003

On the Security of Nested SPN Cipher against the Differential and Linear Cryptanalysis.

Fumihiko Sano, Kenji Ohkuma, Hideo Shimizu, Shinichi Kawamura

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2003

2001

Security Assessment of Hierocrypt and Rijndael against the Differential and Linear Cryptanalysis (Extended Abstract).

Kenji Ohkuma, Hideo Shimizu, Fumihiko Sano, Shin-ichi Kawamura

IACR Cryptol. ePrint Arch., 2001

2000

The Block Cipher Hierocrypt.

Kenji Ohkuma, Hirofumi Muratani, Fumihiko Sano, Shin-ichi Kawamura

Proceedings of the Selected Areas in Cryptography, 7th Annual International Workshop, 2000

Cox-Rower Architecture for Fast Parallel Montgomery Multiplication.

Shin-ichi Kawamura, Masanobu Koike, Fumihiko Sano, Atsushi Shimbo

Proceedings of the Advances in Cryptology, 2000

Performance Evaluation of AES Finalists on the High-End Smart Card.

Fumihiko Sano, Masanobu Koike, Shin-ichi Kawamura, Masue Shiba

Proceedings of the Third Advanced Encryption Standard Candidate Conference, 2000

1998

A 60-mW MPEG4 video codec using clustered voltage scaling with variable supply-voltage scheme.

Masafumi Takahashi, Mototsugu Hamada, Tsuyoshi Nishikawa, Hideho Arakida, Tetsuya Fujita, Fumitoshi Hatori, Shinji Mita, Kojiro Suzuki, Akihiko Chiba, Toshihiro Terazawa, Fumihiko Sano, Yoshinori Watanabe, Kimiyoshi Usami, Mutsunori Igarashi, Takashi Ishikawa, Masahiro Kanazawa, Tadahiro Kuroda, Tohru Furuyama

IEEE J. Solid State Circuits, 1998

Variable supply-voltage scheme for low-power high-speed CMOS digital design.

Tadahiro Kuroda, Kojiro Suzuki, Shinji Mita, Tetsuya Fujita, Fumiyuki Yamane, Fumihiko Sano, Akihiko Chiba, Yoshinori Watanabe, Koji Matsuda, Takeo Maeda, Takayasu Sakurai, Tohru Furuyama

IEEE J. Solid State Circuits, 1998

1996

A 0.9-V, 150-MHz, 10-mW, 4 mm², 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme.

Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Tetsu Nagamatsu, Shinichi Yoshioka, Kojiro Suzuki, Fumihiko Sano, Masayuki Norishima, Masayuki Murota, Makoto Kako, Masaaki Kinugawa, Masakazu Kakurnu, Takayasu Sakurai

IEEE J. Solid State Circuits, 1996