Takayasu Sakurai

According to our database1, Takayasu Sakurai authored at least 164 papers between 1992 and 2018.

Collaborative distances:

Awards

IEEE Fellow

IEEE Fellow 2003, "For contributions to the modeling and design of high speed VLSI circuits.".

Timeline

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Bibliography

2018
Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes.
IEEE Trans. VLSI Syst., 2018

A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017
A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture.
J. Solid-State Circuits, 2017

Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier.
IEICE Transactions, 2017

Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017

Modeling of 3-level buck converters in discontinuous conduction mode for stand-by mode power supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017

2016
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster.
J. Solid-State Circuits, 2016

5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016

56-Level programmable voltage detector in steps of 50mV for battery management.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016

2015
Wireless Power Transfer With Zero-Phase-Difference Capacitance Control.
IEEE Trans. on Circuits and Systems, 2015

16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015

248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting.
Proceedings of the ESSCIRC Conference 2015, 2015

Analysis to optimize sensitivity of RF energy harvester with voltage boost circuit.
Proceedings of the European Conference on Circuit Theory and Design, 2015

2014
Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter.
IEEE Trans. on Circuits and Systems, 2014

1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control.
IEEE Trans. Biomed. Circuits and Systems, 2014

A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS.
J. Solid-State Circuits, 2014

Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.
J. Solid-State Circuits, 2014

92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator.
Proceedings of the Symposium on VLSI Circuits, 2014

An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting.
Proceedings of the ESSCIRC 2014, 2014

2013
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: VDDmin-Aware Dual Supply Voltage Technique.
IEEE Trans. VLSI Syst., 2013

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.
J. Solid-State Circuits, 2013

Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits.
J. Solid-State Circuits, 2013

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits.
J. Solid-State Circuits, 2013

1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme.
Proceedings of the International Symposium on Quality Electronic Design, 2013

Electrical artificial skin using ultraflexible organic transistor.
Proceedings of the 50th Annual Design Automation Conference 2013, 2013

A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS.
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

Variation-aware subthreshold logic circuit design.
Proceedings of the IEEE 10th International Conference on ASIC, 2013

2012
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS.
IEEE Trans. VLSI Syst., 2012

A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation.
IEEE Trans. on Circuits and Systems, 2012

Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. on Circuits and Systems, 2012

A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier.
J. Solid-State Circuits, 2012

An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection.
J. Solid-State Circuits, 2012

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming.
J. Solid-State Circuits, 2012

EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution.
IEICE Transactions, 2012

A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network.
IEICE Transactions, 2012

A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW.
Proceedings of the Symposium on VLSI Circuits, 2012

An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012

A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.
Proceedings of the Symposium on VLSI Circuits, 2012

Ambient electronics and ultra-low power LSI design.
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012

Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm.
Proceedings of the 38th European Solid-State Circuit conference, 2012

Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012

A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. on Circuits and Systems, 2011

A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver.
J. Solid-State Circuits, 2011

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.
J. Solid-State Circuits, 2011

User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects.
J. Solid-State Circuits, 2011

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.
J. Solid-State Circuits, 2011

A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.
IEICE Transactions, 2011

Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.
IEICE Transactions, 2011

0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.
IEICE Transactions, 2011

0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver.
IEICE Transactions, 2011

1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling.
IEICE Transactions, 2011

0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications.
IEICE Transactions, 2011

Beyond the horizon: The next 10x reduction in power - Challenges and solutions.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011

Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Designing ultra-low voltage logic.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011

12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.
Proceedings of the 37th European Solid-State Circuits Conference, 2011

A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates.
Proceedings of the 48th Design Automation Conference, 2011

0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011

An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies.
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2010
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs.
ACM Trans. Design Autom. Electr. Syst., 2010

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
J. Solid-State Circuits, 2010

Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection.
J. Solid-State Circuits, 2010

Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.
IEICE Transactions, 2010

Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories.
IEICE Transactions, 2010

A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS.
IEICE Transactions, 2010

Silicon 3D-integration technology and systems.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

The semiconductor industry in 2025.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

Design of large area electronics with organic transistors.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

Misleading energy and performance claims in sub/near threshold digital systems.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010

0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010

A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's.
Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009
A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet.
IEEE Trans. on Circuits and Systems, 2009

A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems.
IEEE Trans. on Circuits and Systems, 2009

Low Power VLSI Circuit Design with Fine-Grain Voltage Engineering.
IPSJ Trans. System LSI Design Methodology, 2009

An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise.
IEICE Transactions, 2009

A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS.
IEICE Transactions, 2009

A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009

Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009

Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009

A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

A capacitive coupling interface with high sensitivity for wireless wafer testing.
Proceedings of the IEEE International Conference on 3D System Integration, 2009

2008
An 11Gb/s Inductive-Coupling Link with Burst Transmission.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Next-generation power-aware design.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008

Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

1/5 power reduction by global optimization based on fine-grained body biasing.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008

2007
A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's.
IEICE Transactions, 2007

Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link.
IEICE Transactions, 2007

Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines.
IEICE Transactions, 2007

An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors.
IEICE Transactions, 2007

Meeting with the forthcoming IC design.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007

A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future".
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs.
IEEE Trans. VLSI Syst., 2006

Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping.
IEICE Transactions, 2006

A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology.
IEICE Transactions, 2006

Trends of On-Chip Interconnects in Deep Sub-Micron VLSI.
IEICE Transactions, 2006

Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's.
IEICE Transactions, 2006

Compact outside-rail circuit structure by single-cascode two-transistor topology.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

Chip-to-Chip Inductive Wireless Power Transmission System for SiP Applications.
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006

A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
/spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications.
IEEE Trans. Multimedia, 2005

Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction.
Systems and Computers in Japan, 2005

Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's.
IEICE Transactions, 2005

More than two orders of magnitude leakage current reduction in look-up table for FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004
Observation of one-fifth-of-a-clock wake-up time of power-gated circuit.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Cross talk countermeasures in inductive inter-chip wireless superconnect.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
Reshaping EDA for power.
Proceedings of the 40th Design Automation Conference, 2003

2002
Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems.
Journal of Circuits, Systems, and Computers, 2002

Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Minimizing power across multiple technology and design levels.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

2001
Power-conscious Scheduling for Real-time Embedded Systems Design.
VLSI Design, 2001

Estimation of power distribution in VLSI interconnects.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Variable threshold CMOS (VTCMOS) in series connected circuits.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Design methodology and optimization strategy for dual-VTH scheme using commercially available tools.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

An LSI for VDD-hopping and MPEG4 system based on the chip.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Coupling-Driven Bus Design for Low-Power Application-Specific Systems.
Proceedings of the 38th Design Automation Conference, 2001

2000
Analysis and future trend of short-circuit power.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2000

Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control.
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Power Optimization of Real-Time Embedded Systems on Variable Speed Processors.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Run-time voltage hopping for low-power real-time systems.
Proceedings of the 37th Conference on Design Automation, 2000

Design challenges for 0.1um and beyond: embedded tutorial.
Proceedings of ASP-DAC 2000, 2000

Optimization of VDD and VTH for low-power and high speed applications.
Proceedings of ASP-DAC 2000, 2000

Run-time power control scheme using software feedback loop for low-power real-time application.
Proceedings of ASP-DAC 2000, 2000

Compact yet high performance (CyHP) library for short time-to-market with new technologies.
Proceedings of ASP-DAC 2000, 2000

1998
A fine-grain, current mode scheme for VLSI proximity search engine.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998

Integrated Current Sensing Device for Micro IDDQ Test.
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998

Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines.
Proceedings of the ASP-DAC '98, 1998

1996
Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design.
VLSI Signal Processing, 1996

Substrate noise influence on circuit performance in variable threshold-voltage scheme.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1993
High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993

1992
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1992


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