Takayasu Sakurai
According to our database1,
Takayasu Sakurai
authored at least 212 papers
between 1988 and 2022.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2003, "For contributions to the modeling and design of high speed VLSI circuits.".
Timeline
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On csauthors.net:
Bibliography
2022
High-Speed Searching of Optimum Switching Pattern for Digital Active Gate Drive to Adapt to Various Load Conditions.
IEEE Trans. Ind. Electron., 2022
A 6.78-MHz Multiple-Transmitter Wireless Power Transfer System With Efficiency Maximization by Adaptive Magnetic Field Adder IC.
IEEE J. Solid State Circuits, 2022
2021
Analysis and Mitigation of Coupling-Dependent Data Flipping in Wireless Power and Data Transfer System.
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
2019
A 0.90-4.39-V Detection Voltage Range, 56-Level Programmable Voltage Detector Using Fine Voltage-Step Subtraction for Battery Management.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019
An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage.
IEEE J. Solid State Circuits, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Digital Active Gate Drive with Optimal Switching Patterns to Adapt to Sinusoidal Output Current in a Full Bridge Inverter Circuit.
Proceedings of the IECON 2019, 2019
CNN-based Approach for Estimating Degradation of Power Devices by Gate Waveform Monitoring.
Proceedings of the International Conference on IC Design and Technology, 2019
A 500-Mbps Digital Isolator Circuits using Counter-Pulse Immune Receiver Scheme for Power Electronics.
Proceedings of the International Conference on IC Design and Technology, 2019
2018
Clocked Hysteresis Control Scheme With Power-Law Frequency Scaling in Buck Converter to Improve Light-Load Efficiency for IoT Sensor Nodes.
IEEE Trans. Very Large Scale Integr. Syst., 2018
2/3 and 1/2 Reconfigurable Switched Capacitor DC-DC Converter With 92.9% Efficiency at 62 mW/mm<sup>2</sup> Using Driver Amplitude Doubler.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
A 13nW temperature-to-digital converter utilizing sub-threshold MOSFET operation at sub-thermal drain voltage.
Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018
2017
IEEE J. Solid State Circuits, 2017
Design and Analysis of Ultra-Low Power Glitch-Free Programmable Voltage Detector Based on Multiple Voltage Copier.
IEICE Trans. Electron., 2017
Programmable Neuron Array Based on a 2-Transistor Multiplier Using Organic Floating-Gate for Intelligent Sensors.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2017
Modeling of 3-level buck converters in discontinuous conduction mode for stand-by mode power supply.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Buck converter with higher than 87% efficiency over 500nA to 20mA load current range for IoT sensor nodes by Clocked Hysteresis Control.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
2016
Variation-Tolerant Quick-Start-Up CMOS Crystal Oscillator With Chirp Injection and Negative Resistance Booster.
IEEE J. Solid State Circuits, 2016
5.7 A 39.25MHz 278dB-FOM 19µW LDO-free stacked-amplifier crystal oscillator (SAXO) operating at I/O voltage.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2016
2015
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
16.4 Energy-autonomous fever alarm armband integrating fully flexible solar cells, piezoelectric speaker, temperature detector, and 12V organic complementary FET circuits.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
Optimal design to maximize efficiency of single-inductor multiple-output buck converters in discontinuous conduction mode for IoT applications.
Proceedings of the 2015 International Conference on IC Design & Technology, 2015
248pW, 0.11mV/°C glitch-free programmable voltage detector with multiple voltage duplicator for energy harvesting.
Proceedings of the ESSCIRC Conference 2015, 2015
Proceedings of the European Conference on Circuit Theory and Design, 2015
2014
Design Method of Class-F Power Amplifier With Output Power of -20 dBm and Efficient Dual Supply Voltage Transmitter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
1 µm-Thickness Ultra-Flexible and High Electrode-Density Surface Electromyogram Measurement Sheet With 2 V Organic Transistors for Prosthetic Hand Control.
IEEE Trans. Biomed. Circuits Syst., 2014
IEEE J. Solid State Circuits, 2014
Intermittent Resonant Clocking Enabling Power Reduction at Any Clock Frequency for Near/Sub-Threshold Logic Circuits.
IEEE J. Solid State Circuits, 2014
92% start-up time reduction by variation-tolerant chirp injection (CI) and negative resistance booster (NRB) in 39MHz crystal oscillator.
Proceedings of the Symposium on VLSI Circuits, 2014
Flexible, large-area, and distributed organic electronics closely contacted with skin for healthcare applications.
Proceedings of the IEEE 57th International Midwest Symposium on Circuits and Systems, 2014
30.3 Organic-transistor-based 2kV ESD-tolerant flexible wet sensor sheet for biomedical applications with wireless power and data transmission using 13.56MHz magnetic resonance.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
An 85-mV input, 50-µs startup fully integrated voltage multiplier with passive clock boost using on-chip transformers for energy harvesting.
Proceedings of the ESSCIRC 2014, 2014
2013
Minimizing Energy of Integer Unit by Higher Voltage Flip-Flop: V<sub>DDmin</sub>-Aware Dual Supply Voltage Technique.
IEEE Trans. Very Large Scale Integr. Syst., 2013
Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges.
IEEE J. Solid State Circuits, 2013
IEEE J. Solid State Circuits, 2013
Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits.
IEEE J. Solid State Circuits, 2013
Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013
1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Reducing IR drop in 3D integration to less than 1/4 using Buck Converter on Top die (BCT) scheme.
Proceedings of the International Symposium on Quality Electronic Design, 2013
Proceedings of the 50th Annual Design Automation Conference 2013, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013
Proceedings of the IEEE 10th International Conference on ASIC, 2013
2012
On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS.
IEEE Trans. Very Large Scale Integr. Syst., 2012
A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature.
IEEE Trans. Circuits Syst. II Express Briefs, 2012
A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier.
IEEE J. Solid State Circuits, 2012
An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection.
IEEE J. Solid State Circuits, 2012
Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and V<sub>TH</sub>-Tuned Oscillator With Fixed Charge Programming.
IEEE J. Solid State Circuits, 2012
EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution.
IEICE Trans. Electron., 2012
A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network.
IEICE Trans. Electron., 2012
A 0.45-V input on-chip gate boosted (OGB) buck converter in 40-nm CMOS with more than 90% efficiency in load range from 2µW to 50µW.
Proceedings of the Symposium on VLSI Circuits, 2012
An all 0.5V, 1Mbps, 315MHz OOK transceiver with 38-µW career-frequency-free intermittent sampling receiver and 52-µW class-F transmitter in 40-nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2012
A 13.8pJ/Access/Mbit SRAM with charge collector circuits for effective use of non-selected bit line charges.
Proceedings of the Symposium on VLSI Circuits, 2012
Proceedings of Technical Program of 2012 VLSI Design, Automation and Test, 2012
Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in V<sub>DDmin</sub> limited ultra low voltage logic circuits.
Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012
Proceedings of the International Symposium on Low Power Electronics and Design, 2012
2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm.
Proceedings of the 38th European Solid-State Circuit conference, 2012
Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits.
Proceedings of the IEEE 2012 Custom Integrated Circuits Conference, 2012
A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester.
Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012
2011
Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits.
IEEE Trans. Circuits Syst. II Express Briefs, 2011
A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver.
IEEE J. Solid State Circuits, 2011
1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD.
IEEE J. Solid State Circuits, 2011
User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects.
IEEE J. Solid State Circuits, 2011
Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing.
IEEE J. Solid State Circuits, 2011
A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage.
IEICE Trans. Electron., 2011
Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout.
IEICE Trans. Electron., 2011
0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS.
IEICE Trans. Electron., 2011
0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver.
IEICE Trans. Electron., 2011
1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling.
IEICE Trans. Electron., 2011
0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications.
IEICE Trans. Electron., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
Reduction of minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic circuits with post-fabrication automatically selective charge injection.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (V<sub>DD</sub>) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated V<sub>DD</sub> between flip-flops and combinational logics.
Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011
12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains.
Proceedings of the 37th European Solid-State Circuits Conference, 2011
A closed-form expression for estimating minimum operating voltage (V<sub>DDmin</sub>) of CMOS logic gates.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011
A 80-mV input, fast startup dual-mode boost converter with charge-pumped pulse generator for energy harvesting.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS.
Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011
Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011
2010
Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs.
ACM Trans. Design Autom. Electr. Syst., 2010
2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.
IEEE J. Solid State Circuits, 2010
Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection.
IEEE J. Solid State Circuits, 2010
Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits.
IEICE Trans. Electron., 2010
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories.
IEICE Trans. Electron., 2010
A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS.
IEICE Trans. Electron., 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's.
Proceedings of the IEEE International Conference on 3D System Integration, 2010
2009
A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems.
IEEE Trans. Circuits Syst. II Express Briefs, 2009
IEEE J. Solid State Circuits, 2009
IPSJ Trans. Syst. LSI Des. Methodol., 2009
An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise.
IEICE Trans. Electron., 2009
A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS.
IEICE Trans. Electron., 2009
A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2009
Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories.
Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009
Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2009
A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver.
Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories.
Proceedings of the IEEE International Conference on 3D System Integration, 2009
Proceedings of the IEEE International Conference on 3D System Integration, 2009
2008
A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping.
IEEE J. Solid State Circuits, 2008
IEEE J. Solid State Circuits, 2008
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
A 107pJ/b 100kb/s 0.18μm Capacitive-Coupling Transceiver for Printable Communication Sheet.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Increasing minimum operating voltage (V<sub>DDmin</sub>) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators.
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
Solving issues of integrated circuits by 3D-stacking meeting with the era of power, integrity attackers and NRE explosion and a bit of future.
Proceedings of the ESSCIRC 2008, 2008
Experimental assessment of logic circuit performance variability with regular fabrics at 90nm technology node.
Proceedings of the ESSCIRC 2008, 2008
Expected vectorless Teacher-Student Swap (TSS) test method with dual power supply voltages for 0.3V homogeneous multi-core LSI's.
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
Proceedings of the IEEE 2008 Custom Integrated Circuits Conference, 2008
2007
An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display.
IEEE J. Solid State Circuits, 2007
Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs.
IEEE J. Solid State Circuits, 2007
IEEE J. Solid State Circuits, 2007
A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link.
IEEE J. Solid State Circuits, 2007
A Self-Alignment Row-by-Row Variable-<i>V<sub>DD</sub></i> Scheme Reducing 90% of Active-Leakage Power in SRAM's.
IEICE Trans. Electron., 2007
IEICE Trans. Electron., 2007
Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2007
An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors.
IEICE Trans. Electron., 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Design Solutions for a Multi-Object Wireless Power Transmission Sheet Based on Plastic Switches.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
A 0.14pJ/b Inductive-Coupling Inter-Chip Data Transceiver with Digitally-Controlled Precise Pulse Shaping.
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007
A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future".
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007
2006
Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V<sub>DD</sub> LSIs.
IEEE Trans. Very Large Scale Integr. Syst., 2006
$V_rm DD$-Hopping Accelerators for On-Chip Power Supply Circuit to Achieve Nanosecond-Order Transient Time.
IEEE J. Solid State Circuits, 2006
A 195-gb/s 1.2-W inductive inter-chip wireless superconnect with transmit power control scheme for 3-D-stacked system in a package.
IEEE J. Solid State Circuits, 2006
Managing subthreshold leakage in charge-based analog circuits with low-V<sub>TH</sub> transistors by analog T- switch (AT-switch) and super cut-off CMOS (SCCMOS).
IEEE J. Solid State Circuits, 2006
Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-V<sub>TH</sub>/V<sub>DD</sub> and Micro-V<sub>DD</sub>-Hopping.
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
IEICE Trans. Electron., 2006
Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's.
IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2006
An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise Margin.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006
2005
μITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications.
IEEE Trans. Multim., 2005
Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction.
Syst. Comput. Jpn., 2005
Analysis and design of inductive coupling and transceiver circuit for inductive inter-chip wireless superconnect.
IEEE J. Solid State Circuits, 2005
Cut-and-paste customization of organic FET integrated circuit and its application to electronic artificial skin.
IEEE J. Solid State Circuits, 2005
Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-<i>V<sub>DD</sub></i> SRAM's.
IEICE Trans. Electron., 2005
More than two orders of magnitude leakage current reduction in look-up table for FPGAs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Subthreshold-leakage suppressed switched capacitor circuit based on super cut-off CMOS (SCCMOS).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
2004
IEEE J. Solid State Circuits, 2004
Statistical leakage current reduction in high-leakage environments using locality of block activation in time domain.
IEEE J. Solid State Circuits, 2004
Proceedings of the 33rd European Solid-State Circuits Conference, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
VTCMOS characteristics and its optimum conditions predicted by a compact analytical model.
IEEE Trans. Very Large Scale Integr. Syst., 2003
Statistical leakage current reduction by self-timed cut-off scheme for high leakage environments.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
V<sub>TH</sub>-hopping scheme to reduce subthreshold leakage for low-power processors.
IEEE J. Solid State Circuits, 2002
Energy-Constrained V<sub>DD</sub> Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems.
J. Circuits Syst. Comput., 2002
Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology.
Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002
CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002
2001
Design impact of positive temperature dependence on drain current in sub-1-V CMOS VLSIs.
IEEE J. Solid State Circuits, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Design methodology and optimization strategy for dual-VTH scheme using commercially available tools.
Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 38th Design Automation Conference, 2001
Cooperative voltage scaling (CVS) between OS and applications for low-power real-time systems.
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
A super cut-off CMOS (SCCMOS) scheme for 0.5-V supply voltage with picoampere stand-by current.
IEEE J. Solid State Circuits, 2000
Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000
Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session).
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Boosted gate MOS (BGMOS): device/circuit cooperation scheme to achieve leakage-free giga-scale integration.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
Proceedings of ASP-DAC 2000, 2000
Proceedings of ASP-DAC 2000, 2000
Run-time power control scheme using software feedback loop for low-power real-time application.
Proceedings of ASP-DAC 2000, 2000
Compact yet high performance (CyHP) library for short time-to-market with new technologies.
Proceedings of ASP-DAC 2000, 2000
1998
IEEE J. Solid State Circuits, 1998
IEEE J. Solid State Circuits, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, 1998
Proceedings of the ASP-DAC '98, 1998
1996
Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design.
J. VLSI Signal Process., 1996
A swing restored pass-transistor logic-based multiply and accumulate circuit for multimedia applications.
IEEE J. Solid State Circuits, 1996
A 0.9-V, 150-MHz, 10-mW, 4 mm<sup>2</sup>, 2-D discrete cosine transform core processor with variable threshold-voltage (VT) scheme.
IEEE J. Solid State Circuits, 1996
Substrate noise influence on circuit performance in variable threshold-voltage scheme.
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
1994
A 200 MHz 13 mm<sup>2</sup> 2-D DCT macrocell using sense-amplifying pipeline flip-flop scheme.
IEEE J. Solid State Circuits, December, 1994
1993
High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
1992
Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992
1988
Proceedings of the 1988 IEEE International Conference on Computer-Aided Design, 1988