Hisakazu Edamatsu

According to our database, Hisakazu Edamatsu authored at least 4 papers between 1987 and 1998.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1998

Pre-layout Delay Calculation Specification for CMOS ASIC Libraries.

Hisakazu Edamatsu, Katsumi Homma, Masaru Kakimoto, Yutaka Koike, Kinya Tabuchi

Proceedings of the ASP-DAC '98, 1998

1996

Design Methodologies for consumer-use video signal processing LSIs.

Hisakazu Edamatsu, Satoshi Ikawa, Katsuya Hasegawa

Proceedings of the 33st Conference on Design Automation, 1996

1994

Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation.

Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu

IEEE Trans. Computers, 1994

1987

Design of high speed MOS multiplier and divider using redundant binary representation.

Shigeo Kuninobu, Tamotsu Nishiyama, Hisakazu Edamatsu, Takashi Taniguchi, Naofumi Takagi

Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987