Naofumi Takagi

According to our database1, Naofumi Takagi authored at least 82 papers between 1982 and 2019.

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Bibliography

2019
Concurrent Error Detectable Carry Select Adder with Easy Testability.
IEEE Trans. Computers, 2019

Conversion of Logic Gates in Netlists for Rapid Single Flux Quantum Circuits Utilizing Confluence of Pulses.
IPSJ Trans. System LSI Design Methodology, 2019

mROS: A Lightweight Runtime Environment for Robot Software Components onto Embedded Devices.
Proceedings of the 10th International Symposium on Highly-Efficient Accelerators and Reconfigurable Technologies, 2019

2018
Algorithms for Evaluating the Matrix Polynomial I+A+A2+...+AN-1 with Reduced Number of Matrix Multiplications.
IEICE Transactions, 2018

Design concept of a lightweight runtime environment for robot software components onto embedded devices: work-in-progress.
Proceedings of the International Conference on Embedded Software, 2018

2017
Floating-Point Multiplier with Concurrent Error Detection Capability by Partial Duplication.
IEICE Transactions, 2017

Recap of the 22nd Asia and South- Pacific Design Automation Conference.
IEEE Design & Test, 2017

2016
RSFQ 4-bit Bit-Slice Integer Multiplier.
IEICE Transactions, 2016

High-Throughput Rapid Single-Flux-Quantum Circuit Implementations for Exponential and Logarithm Computation Using the Radix-2 Signed-Digit Representation.
IEICE Transactions, 2016

An evaluation framework of OS-level power managements for the big.LITTLE architecture.
Proceedings of the 14th IEEE International New Circuits and Systems Conference, 2016

2015
An Allocation Optimization Method for Partially-reliable Scratch-pad Memory in Embedded Systems.
IPSJ Trans. System LSI Design Methodology, 2015

A Verification Method for Single-Flux-Quantum Circuits Using Delay-Based Time Frame Model.
IEICE Transactions, 2015

2014
Circuit Description and Design Flow of Superconducting SFQ Logic Circuits.
IEICE Transactions, 2014

Nested Loop Parallelization Using Polyhedral Optimization in High-Level Synthesis.
IEICE Transactions, 2014

Design and High-Speed Demonstration of Single-Flux-Quantum Bit-Serial Floating-Point Multipliers Using a 10kA/cm2 Nb Process.
IEICE Transactions, 2014

Nb 9-Layer Fabrication Process for Superconducting Large-Scale SFQ Circuits and Its Process Evaluation.
IEICE Transactions, 2014

A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits.
IEICE Transactions, 2014

Large-Scale Integrated Circuit Design Based on a Nb Nine-Layer Structure for Reconfigurable Data-Path Processors.
IEICE Transactions, 2014

An Operation Scenario Model for Energy Harvesting Embedded Systems and an Algorithm to Maximize the Operation Quality.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

2013
Low-Overhead Fault-Secure Parallel Prefix Adder by Carry-Bit Duplication.
IEICE Transactions, 2013

A Buffering Method for Parallelized Loop with Non-Uniform Dependencies in High-Level Synthesis.
Proceedings of the Algorithms and Architectures for Parallel Processing, 2013

2012
A VLSI Architecture with Multiple Fast Store-Based Block Parallel Processing for Output Probability and Likelihood Score Computations in HMM-Based Isolated Word Recognition.
IEICE Transactions, 2012

A C-Testable Multiple-Block Carry Select Adder.
IEICE Transactions, 2012

2011
Partial Product Generation Utilizing the Sum of Operands for Reduced Area Parallel Multipliers.
IPSJ Trans. System LSI Design Methodology, 2011

Layout-Driven Skewed Clock Tree Synthesis for Superconducting SFQ Circuits.
IEICE Transactions, 2011

2010
100 GHz Demonstrations Based on the Single-Flux-Quantum Cell Library for the 10 kA/cm2 Nb Multi-Layer Process.
IEICE Transactions, 2010

Automated Passive-Transmission-Line Routing Tool for Single-Flux-Quantum Circuits Based on A* Algorithm.
IEICE Transactions, 2010

Comparisons of Synchronous-Clocking SFQ Adders.
IEICE Transactions, 2010

A VLSI Architecture for Output Probability Computations of HMM-Based Recognition Systems with Store-Based Block Parallel Processing.
IEICE Transactions, 2010

A C-Testable 4-2 Adder Tree for an Easily Testable High-Speed Multiplier.
IEICE Transactions, 2010

2009
Fast Hardware Algorithm for Division in hbox 2m Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions.
IEEE Trans. on Circuits and Systems, 2009

2008
A Combined Circuit for Multiplication and Inversion in GF(2m).
IEEE Trans. on Circuits and Systems, 2008

Bipartite Modular Multiplication Method.
IEEE Trans. Computers, 2008

Proposal of a Desk-Side Supercomputer with Reconfigurable Data-Paths Using Rapid Single-Flux-Quantum Circuits.
IEICE Transactions, 2008

A Clock Scheduling Algorithm for High-Throughput RSFQ Digital Circuits.
IEICE Transactions, 2008

Fast and memory efficient VLSI architecture for output probability computations of HMM-based recognition systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Level-Testability of Multi-operand Adders.
Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007
A Method of Sequential Circuit Synthesis Using One-Hot Encoding for Single-Flux-Quantum Digital Circuits.
IEICE Transactions, 2007

Logic Synthesis Method for Dual-Rail RSFQ Digital Circuits Using Root-Shared Binary Decision Diagrams.
IEICE Transactions, 2007

An Algorithm for Inversion in GF(2^m) Suitable for Implementation Using a Polynomial Multiply Instruction on GF(2).
Proceedings of the 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 2007

2006
A Hardware Algorithm for Integer Division Using the SD2 Representation.
IEICE Transactions, 2006

Hardware Algorithm for Computing Reciprocal of Euclidean Norm of a 3-D Vector.
IEICE Transactions, 2006

2005
A Hardware Algorithm for Modular Multiplication/Division.
IEEE Trans. Computers, 2005

A Hardware Algorithm for Modular Multiplication/Division Based on the Extended Euclidean Algorithm.
IEICE Transactions, 2005

Bipartite Modular Multiplication.
Proceedings of the Cryptographic Hardware and Embedded Systems - CHES 2005, 7th International Workshop, Edinburgh, UK, August 29, 2005

A Hardware Algorithm for Integer Division.
Proceedings of the 17th IEEE Symposium on Computer Arithmetic (ARITH-17 2005), 2005

2004
Systematic IEEE rounding method for high-speed floating-point multipliers.
IEEE Trans. VLSI Syst., 2004

2003
A VLSI Algorithm for Modular Multiplication/Division.
Proceedings of the 16th IEEE Symposium on Computer Arithmetic (Arith-16 2003), 2003

2002
Special Session: Security on SoC.
Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Multiple-Valued-Digit Number Representations in Arithmetic Circuit Algorithms.
Proceedings of the 32nd IEEE International Symposium on Multiple-Valued Logic (ISMVL 2002), 2002

2001
A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis.
IEEE Trans. Computers, 2001

A Hardware Algorithm for Computing Reciprocal Square Root.
Proceedings of the 15th IEEE Symposium on Computer Arithmetic (Arith-15 2001), 2001

2000
A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector.
IEEE Trans. Computers, 2000

A fast addition algorithm for elliptic curve arithmetic in GF(2n) using projective coordinates.
Inf. Process. Lett., 2000

1999
Adders.
Proceedings of the VLSI Handbook., 1999

Dividers.
Proceedings of the VLSI Handbook., 1999

Multipliers.
Proceedings of the VLSI Handbook., 1999

A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival.
IEEE Trans. Computers, 1999

Digit-Recurrence Algorithm for Computing Euclidean Norm of a 3-D Vector.
Proceedings of the 14th IEEE Symposium on Computer Arithmetic (Arith-14 '99), 1999

1998
Powering by a Table Look-Up and a Multiplication with Operand Modification.
IEEE Trans. Computers, 1998

1997
Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification.
IEEE Trans. Computers, 1997

O(n)-Depth Modular Exponentiation Circuit Algorithm.
IEEE Trans. Computers, 1997

Generating a Power of an Operand by a Table Look-up and a Multiplication.
Proceedings of the 13th Symposium on Computer Arithmetic (ARITH-13 '97), 1997

1996
Square Rooting by Iterative Multiply-Additions.
Inf. Process. Lett., 1996

1995
A Multiple-Precision Modular Multiplication Algorithm with Triangle Additions.
IEICE Transactions, 1995

Efficient Initial Approximation and Fast Converging Methods for Division and Square Root.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

Function Evaluation by Table Look-up and Addition.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

O(n)-depth circuit algorithm for modular exponentiation.
Proceedings of the 12th Symposium on Computer Arithmetic (ARITH-12 '95), 1995

1992
Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem.
IEEE Trans. Computers, 1992

A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation.
IEEE Trans. Computers, 1992

1991
Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation.
IEEE Trans. Computers, 1991

An on-line error-detectable high-speed array divider.
Systems and Computers in Japan, 1991

A radix-4 modular multiplication hardware algorithm efficient for iterative modular multiplications.
Proceedings of the 10th IEEE Symposium on Computer Arithmetic, 1991

1988
An on-line error-detectable array divider with a redundant binary representation and a residue code.
Proceedings of the Eighteenth International Symposium on Fault-Tolerant Computing, 1988

1987
On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic.
IEEE Trans. Computers, 1987

On high-speed parallel algorithms using redundant coding.
Systems and Computers in Japan, 1987

A hardware algorithm for computing sine and cosine using redundant binary representation.
Systems and Computers in Japan, 1987

Design of high speed MOS multiplier and divider using redundant binary representation.
Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1986
Hardware algorithms for computing exponentials and logarithms using redundant binary representation.
Systems and Computers in Japan, 1986

A square root hardware algorithm using redundant binary representation.
Systems and Computers in Japan, 1986

1985
High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree.
IEEE Trans. Computers, 1985

1982
The Parallel Enumeration Sorting Scheme for VLSI.
IEEE Trans. Computers, 1982


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