Hisatada Miyatake

According to our database1, Hisatada Miyatake authored at least 2 papers between 1996 and 2001.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2001
A design for high-speed low-power CMOS fully parallel content-addressable memory macros.
IEEE J. Solid State Circuits, 2001

1996
A parallel processing chip with embedded DRAM macros.
IEEE J. Solid State Circuits, 1996


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