Eric Retter

According to our database, Eric Retter authored at least 3 papers between 1995 and 2018.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2018

IBM POWER9 memory architectures for optimized systems.

William J. Starke, J. S. Dodson, Jeffrey Stuecheli, Eric Retter, Brad W. Michael, Stephen J. Powell, James A. Marcella

IBM J. Res. Dev., 2018

1996

A parallel processing chip with embedded DRAM macros.

Toshio Sunaga, Hisatada Miyatake, Koji Kitamura, Peter M. Kogge, Eric Retter

IEEE J. Solid State Circuits, 1996

1995

Combined DRAM and logic chip for massively parallel systems.

Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter

Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI '95), 1995