Hosahalli R. Srinivas

According to our database, Hosahalli R. Srinivas authored at least 10 papers between 1992 and 1999.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

1999

A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture.

Hosahalli R. Srinivas, Keshab K. Parhi

J. VLSI Signal Process., 1999

1998

VLSI Implementation of a 300-MHz 0.35 um CMOS 32-bit Auto-Reloadable Binary Synchronous Counter with Optimal Test Overhead Delay.

S. K. Misra, R. K. Kolagotla, Hosahalli R. Srinivas, J. C. Mo, Marc S. Diamondstein

Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998

1997

Radix 2 Division with Over-Redundant Quotient Selection.

Hosahalli R. Srinivas, Keshab K. Parhi, Luis A. Montalvo

IEEE Trans. Computers, 1997

Half-rate GSM vocoder implementation on a dual mac digital signal processor.

Mohit K. Prasad, Paul D'Arcy, Arup Gupta, Marc S. Diamondstein, Hosahalli R. Srinivas

Proceedings of the 1997 IEEE International Conference on Acoustics, 1997

1995

A Fast Radix-4 Division Algorithm and Its Architecture.

Hosahalli R. Srinivas, Keshab K. Parhi

IEEE Trans. Computers, 1995

A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.

W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi

Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995

A floating point radix 2 shared division/square root chip.

Hosahalli R. Srinivas, Keshab K. Parhi

Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995

1994

A C-testable carry-free divider.

Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi

IEEE Trans. Very Large Scale Integr. Syst., 1994

A Fast Radix-4 Division Algorithm.

Hosahalli R. Srinivas, Keshab K. Parhi

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

1992

High-speed VLSI arithmetic processor architectures using hybrid number representation.

Hosahalli R. Srinivas, Keshab K. Parhi

J. VLSI Signal Process., 1992