Bapiraju Vinnakota

According to our database, Bapiraju Vinnakota authored at least 53 papers between 1990 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

SCIP to the Next Generation of Computing: Extending More than Moore with Silicon Photonics Chiplets in Package (SCIP).

Vivek Raghunathan, Karl Muth, Bapiraju Vinnakota, Prasad Venugopal, Rebecca Schaevitz, Manish Mehta

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

2021

The Open Domain-Specific Architecture.

Bapiraju Vinnakota, Ishwar Agarwal, Kevin Drucker, Dharmesh Jani, Gary Miller, Millind Mittal, Robert Wang

IEEE Micro, 2021

An Open Inter-Chiplet Communication Link: Bunch of Wires (BoW).

Shahab Ardalan, Ramin Farjadrad, Mark Kuemerle, Ken Poulton, Suresh Subramaniam, Bapiraju Vinnakota

IEEE Micro, 2021

The Open Domain-Specific Architecture: Next Steps to Production.

Bapiraju Vinnakota

Proceedings of the NANOCOM '21: The Eighth Annual ACM International Conference on Nanoscale Computing and Communication, Virtual Event, Italy, September 7, 2021

2020

Bunch of Wires: An Open Die-to-Die Interface.

Shahab Ardalan, Halil Cirit, Ramin Farjad-Rad, Mark Kuemerle, Ken Poulton, Suresh Subramanian, Bapiraju Vinnakota

Proceedings of the IEEE Symposium on High-Performance Interconnects, 2020

2019

High Capacity On-Package Physical Link Considerations.

Greg Taylor, Ramin Farjadrad, Bapiraju Vinnakota

Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

A Bunch of Wires (BoW) Interface for Inter-Chiplet Communication.

Ramin Farjadrad, Bapiraju Vinnakota

Proceedings of the 2019 IEEE Symposium on High-Performance Interconnects, 2019

2004

Combining dictionary coding and LFSR reseeding for test data compression.

Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota

Proceedings of the 41th Design Automation Conference, 2004

A digital DFT technique for verifying the static performance of A/D converters.

Wooyoung Choi, Bapiraju Vinnakota, Ramesh Harjani

Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003

Development of Energy Consumption Ratio Test.

Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota

Proceedings of the 21st IEEE VLSI Test Symposium (VTS 2003), 27 April, 2003

Test Vector Generation Based on Correlation Model for Ratio-Iddq.

Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

2002

Statistical threshold formulation for dynamic I_dd test.

Wanli Jiang, Bapiraju Vinnakota

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

2001

Defect-oriented test scheduling.

Wanli Jiang, Bapiraju Vinnakota

IEEE Trans. Very Large Scale Integr. Syst., 2001

Current Measurement for Dynamic Idd Test.

Xiaoyun Sun, Bapiraju Vinnakota

Proceedings of the 19th IEEE VLSI Test Symposium (VTS 2001), Test and Diagnosis in a Nanometric World, 29 April, 2001

Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter.

Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

High Performance Parallel Fault Simulation.

Amit K. Varshney, Bapiraju Vinnakota, Eric Skuldt, Brion L. Keller

Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Crosstalk Fault Detection by Dynamic Idd.

Xiaoyun Sun, Seonki Kim, Bapiraju Vinnakota

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

2000

DFT for digital detection of analog parametric faults in SC filters.

Bapiraju Vinnakota, Ramesh Harjani

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

IC test using the energy consumption ratio.

Wanli Jiang, Bapiraju Vinnakota

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Biomedical ICs: What is Different about Testing those ICs?

Bapiraju Vinnakota, André Ivanov

Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000

An analysis of the delay defect detection capability of the ECR test method.

Seonki Kim, Sreejit Chakravarty, Bapiraju Vinnakota

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

Fast Test Application Technique Without Fast Scan Clocks.

Seonki Kim, Bapiraju Vinnakota

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Optimal test-set generation for parametric fault detection in switched capacitor filters.

Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota

Proceedings of the 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, 2000

1999

Data parallel fault simulation.

Minesh B. Amin, Bapiraju Vinnakota

IEEE Trans. Very Large Scale Integr. Syst., 1999

Statistical threshold formulation for dynamic I_dd test.

Wanli Jiang, Bapiraju Vinnakota

Proceedings of the Proceedings IEEE International Test Conference 1999, 1999

Deep submicron defect detection with the energy consumption ratio.

Bapiraju Vinnakota

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Digital Aetection of Analog Parametric Faults in SC Filters.

Ramesh Harjani, Bapiraju Vinnakota

Proceedings of the 36th Conference on Design Automation, 1999

Digital detection of parametric faults in data converters.

Bapiraju Vinnakota, Ramesh Harjani

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1998

Fast fault translation.

Bapiraju Vinnakota, Jason Andrews

IEEE Trans. Very Large Scale Integr. Syst., 1998

Process-tolerant test with energy consumption ratio.

Bapiraju Vinnakota, Wanli Jiang, Dechang Sun

Proceedings of the Proceedings IEEE International Test Conference 1998, 1998

Fast State Verification.

Dechang Sun, Bapiraju Vinnakota, Wanli Jiang

Proceedings of the 35th Conference on Design Automation, 1998

1997

Monitoring Power Dissipation for Fault Detection.

Bapiraju Vinnakota

J. Electron. Test., 1997

Workload Distribution in Fault Simulation.

Minesh B. Amin, Bapiraju Vinnakota

J. Electron. Test., 1997

Pseudoduplication - An ACOB Technique for Single-Ended Circuits.

Bapiraju Vinnakota, Ramesh Harjani, Wooyoung Choi

Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997

1996

System-level design for test of fully differential analog circuits.

Nicholas J. Stessman, Bapiraju Vinnakota, Ramesh Harjani

IEEE J. Solid State Circuits, 1996

ZAMBEZI: a parallel pattern parallel fault sequential circuit fault simulator.

Minesh B. Amin, Bapiraju Vinnakota

Proceedings of the 14th IEEE VLSI Test Symposium (VTS'96), April 28, 1996

Mixed-Signal Design for Test.

Bapiraju Vinnakota, Ramesh Harjani

Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996

Zamlog: a parallel algorithm for fault simulation based on Zambezi.

Minesh B. Amin, Bapiraju Vinnakota

Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

1995

Implementing Multiplication with Split Read-Only Memory.

Bapiraju Vinnakota

IEEE Trans. Computers, 1995

Reducing test application time in scan design schemes.

Bapiraju Vinnakota, Nicholas J. Stessman

Proceedings of the 13th IEEE VLSI Test Symposium (VTS'95), April 30, 1995

1994

A C-testable carry-free divider.

Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi

IEEE Trans. Very Large Scale Integr. Syst., 1994

Design of Algorithm-Based Fault-Tolerant Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.

Bapiraju Vinnakota, Niraj K. Jha

IEEE Trans. Parallel Distributed Syst., 1994

Generation of All Reed-Muller Expansions of a Switching Function.

Bapiraju Vinnakota, V. V. Bapeswara Rao

IEEE Trans. Computers, 1994

Enumeration of Binary Trees.

Bapiraju Vinnakota, V. V. Bapeswara Rao

Inf. Process. Lett., 1994

Analog circuit observer blocks.

Ramesh Harjani, Bapiraju Vinnakota

Proceedings of the 12th IEEE VLSI Test Symposium (VTS'94), 1994

The Design of Analog Self-Checking Circuits.

Bapiraju Vinnakota, Ramesh Harjani

Proceedings of the Seventh International Conference on VLSI Design, 1994

Functional Test Generation for FSMs by Fault Extraction.

Bapiraju Vinnakota, Jason Andrews

Proceedings of the 31st Conference on Design Automation, 1994

1993

Synthesis of Algorithm-Based Fault-Tolerant Systems from Dependence Graphs.

Bapiraju Vinnakota, Niraj K. Jha

IEEE Trans. Parallel Distributed Syst., 1993

Diagnosability and Diagnosis of Algorithm-Based Fault-Tolerant Systems.

Bapiraju Vinnakota, Niraj K. Jha

IEEE Trans. Computers, 1993

1992

Repair of RAMs With Clustered Faults.

Bapiraju Vinnakota, Jason Andrews

Proceedings of the Proceedings 1992 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1992

1991

Design of Multiprocessor Systems for Concurrent Error Detection and Fault Diagnosis.

Bapiraju Vinnakota, Niraj K. Jha

Proceedings of the 1991 International Symposium on Fault-Tolerant Computing, 1991

MACHETE: synthesis of sequential machines for easy testability.

Bapiraju Vinnakota, Niraj K. Jha

Proceedings of the conference on European design automation, 1991

1990

A dependence graph-based approach to the design of algorithm-based fault tolerant systems.

Bapiraju Vinnakota, Niraj K. Jha

Proceedings of the 20th International Symposium on Fault-Tolerant Computing, 1990