Keshab K. Parhi
According to our database^{1},
Keshab K. Parhi
authored at least 403 papers
between 1989 and 2019.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1996, "For contributions to the fields of VLSI digital signal processing architectures, design methodologies and tools.".
Timeline
Legend:
Book In proceedings Article PhD thesis OtherLinks
Homepages:

at orcid.org
On csauthors.net:
Bibliography
2019
Architecture Optimization and Performance Comparison of NonceMisuseResistant Authenticated Encryption Algorithms.
IEEE Trans. VLSI Syst., 2019
RETOUCH: The Retinal OCT Fluid Detection and Segmentation Benchmark and Challenge.
IEEE Trans. Med. Imaging, 2019
Computing Arithmetic Functions Using Stochastic Logic by Series Expansion.
IEEE Trans. Emerging Topics Comput., 2019
Discriminative Ratio of Spectral Power and Relative Power Features Derived via FrequencyDomain Model Ratio With Application to Seizure Prediction.
IEEE Trans. Biomed. Circuits and Systems, 2019
Effect of Finite WordLength on SQNR, Area and Power for RealValued Serial FFT.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
FeedForward XOR PUFs: Reliability and AttackResistance Analysis.
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Computing Radial Basis Function Support Vector Machine using DNA via Fractional Coding.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
2018
LinearPhase Lattice FIR Digital Filter Architectures Using Stochastic Logic.
Signal Processing Systems, 2018
Canonic Composite Length RealValued FFT.
Signal Processing Systems, 2018
KeyBased Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered ModeBased Design.
IEEE Trans. Information Forensics and Security, 2018
Stochastic Logic Implementations of Polynomials With All Positive Coefficients by Expansion Methods.
IEEE Trans. on Circuits and Systems, 2018
A Serial Commutator Fast Fourier Architecture for RealValued Signals.
IEEE Trans. on Circuits and Systems, 2018
Fully Automated Segmentation of Fluid/Cyst Regions in Optical Coherence Tomography Images With Diabetic Macular Edema Using Neutrosophic Sets and Graph Algorithms.
IEEE Trans. Biomed. Engineering, 2018
IncrementalPrecision Based Feature Computation and MultiLevel Classification for LowEnergy InternetofThings.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
PermDNN: Efficient Compressed DNN Architecture with Permuted Diagonal Matrices.
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
A Physical Unclonable Function based on Capacitor Mismatch in a ChargeRedistribution SARADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Predicting SoftResponse of MUX PUFs via Logistic Regression of Total Delay Difference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
LowEnergy Architectures of Linear Classifiers for IoT Applications using Incremental Precision and MultiLevel Classification.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
OCT Fluid Segmentation using Graph Shortest Path and Convolutional Neural Network^{*}.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Classifying Treated vs. Untreated MDD Adolescents from Anatomical Connectivity using Nonlinear SVM.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Anatomical Biomarkers for Adolescent Major Depressive Disorder from Diffusion Weighted Imaging using SVM Classifier.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Biomarkers for Adolescent MDD from Anatomical Connectivity and Network Topology Using Diffusion MRI.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Effect of aging on linear and nonlinear MUX PUFs by statistical modeling.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Constrained Tensor Decomposition Optimization With Applications To Fmri Data Analysis.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
Classifying Adolescent Major Depressive Disorder using Linear SVM with Anatomical Features from Diffusion Weighted Imaging.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
Altered Structural Connection Between Hippocampus and Insula in Adolescent Major Depressive Disorder using DTI.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
LLRBased SuccessiveCancellation List Decoder for Polar Codes With Multibit Decision.
IEEE Trans. on Circuits and Systems, 2017
Reliable PUFBased Local Authentication With SelfCorrection.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2017
VLSI Architectures for the Restricted Boltzmann Machine.
JETC, 2017
Computing Polynomials Using Unipolar Stochastic Logic.
JETC, 2017
Canonic FFT flow graphs for realvalued even/odd symmetric inputs.
EURASIP J. Adv. Sig. Proc., 2017
A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Analysis of stochastic logic circuits in unipolar, bipolar and hybrid formats.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
An entropy test for determining whether a MUX PUF is linear or nonlinear.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Hierarchical functional obfuscation of integratec circuits using a modebased approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
FPGA implementation and comparison of AESGCM and Deoxys authenticated encryption schemes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Extraction of common task signals and spatial maps from group fMRI using a PARAFACbased tensor decomposition technique.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
Computing Polynomials with Positive Coefficients using Stochastic Logic by DoubleNAND Expansion.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements.
Proceedings of the 54th Annual Design Automation Conference, 2017
A DRAM based physical unclonable function capable of generating >10^{32} Challenge Response Pairs per 1Kbit array for secure chip authentication.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Molecular computation of complex Markov chains with selfloop state transitions.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
Functional encryption of integrated circuits by keybased hybrid obfuscation.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
Performance comparison of AESGCMSIV and AESGCM algorithms for authenticated encryption on FPGA platforms.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
Architectures for Recursive Digital Filters Using Stochastic Computing.
IEEE Trans. Signal Processing, 2016
Optic Disc Boundary and Vessel Origin Segmentation of Fundus Images.
IEEE J. Biomedical and Health Informatics, 2016
LowComplexity Seizure Prediction From iEEG/sEEG Using Spectral Power and Ratios of Spectral Power.
IEEE Trans. Biomed. Circuits and Systems, 2016
Beat Frequency DetectorBased HighSpeed True Random Number Generators: Statistical Modeling and Analysis.
JETC, 2016
Computing RBF Kernel for SVM Classification Using Stochastic Logic.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
DataCanonic Real FFT FlowGraphs for Composite Lengths.
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Soft Response Generation and Thresholding Strategies for Linear and FeedForward MUX PUFs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Belief propagation decoding of polar codes using stochastic computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Machine learning classifiers using stochastic logic.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Modebased Obfuscation using ControlFlow Modifications.
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016
Computing Complex Functions using Factorization in Unipolar Stochastic Logic.
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Computing Polynomials by Chemical Reaction Networks.
Proceedings of the 2016 IEEE Global Communications Conference, 2016
Artery/vein classification of retinal blood vessels using feature selection.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Classification of obsessivecompulsive disorder from restingstate fMRI.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Automated detection of neovascularization for proliferative diabetic retinopathy screening.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Estimating delay differences of arbiter PUFs using silicon data.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Seizure prediction using longterm fragmented intracranial canine and human EEG recordings.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Synthesis of correlated bit streams for stochastic computing.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Computing hyperbolic tangent and sigmoid functions using stochastic logic.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
LowLatency SuccessiveCancellation List Decoders for Polar Codes With Multibit Decision.
IEEE Trans. VLSI Syst., 2015
Obfuscating DSP Circuits via HighLevel Transformations.
IEEE Trans. VLSI Syst., 2015
Molecular Sensing and Computing Systems.
TMBMC, 2015
Blood Vessel Segmentation of Fundus Images by Major Vessel Extraction and Subimage Classification.
IEEE J. Biomedical and Health Informatics, 2015
Iterative Vessel Segmentation of Fundus Images.
IEEE Trans. Biomed. Engineering, 2015
Early Seizure Detection Using Neuronal Potential Similarity: A Generalized LowComplexity and Robust Measure.
Int. J. Neural Syst., 2015
Joint brain connectivity estimation from diffusion and functional MRI data.
Proceedings of the Medical Imaging 2015: Image Processing, 2015
Successive cancellation decoding of polar codes using stochastic computing.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Faulttolerant ripplecarry binary adder using partial triple modular redundancy (PTMR).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Markov chain computations using molecular reactions.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Effect of bitlevel correlation in stochastic computing.
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
An obfuscated radix2 real FFT architecture.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Lattice FIR digital filter architectures using stochastic computing.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Serial and interleaved architectures for computing real FFT.
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Reducedlatency LLRbased SC List Decoder for Polar Codes.
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Seizure detection using regression tree based feature selection and polynomial SVM classification.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Seizure prediction using polynomial SVM classification.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
3D localization of Diabetic Macular Edema using OCT thickness maps.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Seizure prediction using crosscorrelation and classification.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
Architectures for stochastic normalized and modified lattice IIR filters.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
Canonic realvalued radix2n FFT computations.
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
Impulse Noise Correction in OFDM Systems.
Signal Processing Systems, 2014
Early Stopping Criteria for EnergyEfficient LowLatency BeliefPropagation Polar Code Decoders.
IEEE Trans. Signal Processing, 2014
DREAM: Diabetic Retinopathy Analysis Using Machine Learning.
IEEE J. Biomedical and Health Informatics, 2014
Latency Analysis and Architecture Design of Simplified SC Polar Decoders.
IEEE Trans. on Circuits and Systems, 2014
LowLatency SuccessiveCancellation Polar Decoder Architectures Using 2Bit Decoding.
IEEE Trans. on Circuits and Systems, 2014
LowComplexity Welch Power Spectral Density Computation.
IEEE Trans. on Circuits and Systems, 2014
Statistical Analysis of MUXBased Physical Unclonable Functions.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2014
Interleaved successive cancellation polar decoders.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Architectures for polar BP decoders using folding.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Architectures for IIR digital filters using stochastic computing.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Protecting DSP circuits through obfuscation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
VLSI systems for neurocomputing and health informatics.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA  May 21, 2014
Seizure detection using wavelet decomposition of the prediction error signal from a single channel of intracranial EEG.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
Classification of borderline personality disorder based on spectral power of restingstate fMRI.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
Robust and low complexity algorithms for seizure detection.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
True Random Number Generator circuits based on single and multiphase beat frequency detection.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Algorithm and architecture for hybrid decoding of polar codes.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Successive cancellation list polar decoder using loglikelihood ratios.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Asynchronous discretetime signal processing with molecular reactions.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Canonic realvalued FFT structures.
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Signal Flow Graphs and Data Flow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2013
Design and Optimization of Multiplierless FIR Filters Using SubThreshold Circuits.
Signal Processing Systems, 2013
Comments on "Lowenergy CSMT carry generators and binary adders".
IEEE Trans. VLSI Syst., 2013
LowLatency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder.
IEEE Trans. Signal Processing, 2013
Pipelined Architectures for RealValued FFT and HermitianSymmetric IFFT With Real Datapaths.
IEEE Trans. on Circuits and Systems, 2013
Hierarchical Folding and Synthesis of Iterative Data Flow Graphs.
IEEE Trans. on Circuits and Systems, 2013
FFT Architectures for RealValued Signals Based on Radix2^{3} and Radix2^{4} Algorithms.
IEEE Trans. on Circuits and Systems, 2013
An InPlace FFT Architecture for RealValued Signals.
IEEE Trans. on Circuits and Systems, 2013
Optimized joint timing synchronization and channel estimation for communications systems with multiple transmit antennas.
EURASIP J. Adv. Sig. Proc., 2013
Performance evaluation of variable transmission rate OFDM systems via network source coding.
EURASIP J. Adv. Sig. Proc., 2013
Semiblind frequencydomain timing synchronization and channel estimation for OFDM systems.
EURASIP J. Adv. Sig. Proc., 2013
Digital logic with molecular reactions.
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2013
Architecture optimizations for BP polar decoders.
Proceedings of the IEEE International Conference on Acoustics, 2013
Architectures for digital filters using stochastic computing.
Proceedings of the IEEE International Conference on Acoustics, 2013
Automated localization of cysts in diabetic macular edema using optical coherence tomography images.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Seizure prediction with bipolar spectral power features using Adaboost and SVM classifiers.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Schizophrenia classification with singletrial MEG during language processing.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Automated denoising and segmentation of optical coherence tomography images.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Lowenergy architectures for Support Vector Machine computation.
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
Optimized Joint Timing Synchronization and Channel Estimation for OFDM Systems.
IEEE Wireless Commun. Letters, 2012
Pipelined Parallel FFT Architectures via Folding Transformation.
IEEE Trans. VLSI Syst., 2012
A NetworkEfficient Nonbinary QCLDPC Decoder Architecture.
IEEE Trans. on Circuits and Systems, 2012
Static and dynamic information derived from source and system features for person recognition from humming.
I. J. Speech Technology, 2012
Digital Signal Processing With Molecular Reactions.
IEEE Design & Test of Computers, 2012
Variable data rate (VDR) network congestion control (NCC) applied to voice/audio communication.
Computer Networks, 2012
Reducedlatency SC polar decoder architectures.
Proceedings of IEEE International Conference on Communications, 2012
Efficient folded VLSI architectures for linear prediction error filters.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Parallel pipelined FFT architectures with reduced number of delays.
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Selection of abnormal neural oscillation patterns associated with sentencelevel language disorder in Schizophrenia.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Seizure detection on/off system using rats' ECoG.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Low complexity algorithm for seizure prediction using Adaboost.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Screening fundus images for diabetic retinopathy.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Reducing the number of features for seizure prediction of spectral power in intracranial EEG.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Session TP8b2: Biomedical signal and image processing.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Verifying equivalence of digital signal processing circuits.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
HighSpeed Parallel Architectures for Linear Feedback Shift Registers.
IEEE Trans. Signal Processing, 2011
Secure Variable Data Rate Transmission.
IEEE Trans. on Circuits and Systems, 2011
Power Reduction in FrequencySelective FIR Filters Under Voltage Overscaling.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
Combining Evidence from Spectral and SourceLike Features for Person Recognition from Humming.
Proceedings of the INTERSPEECH 2011, 2011
A low complexity seizure prediction algorithm.
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Synchronous sequential computation with molecular reactions.
Proceedings of the 48th Design Automation Conference, 2011
Asynchronous computation with molecular reactions.
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
Fast Reconfigurable Elliptic Curve Cryptography Acceleration for GF(2^{m}) on 32 bit Processors.
Signal Processing Systems, 2010
LowComplexity Switch Network for Reconfigurable LDPC Decoders.
IEEE Trans. VLSI Syst., 2010
Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage.
IEEE Trans. VLSI Syst., 2010
MinSum Decoder Architectures With Reduced Word Length for LDPC Codes.
IEEE Trans. on Circuits and Systems, 2010
Writing and Compiling Code into Biochemistry.
Proceedings of the Biocomputing 2010: Proceedings of the Pacific Symposium, 2010
A synthesis flow for digital signal processing with biomolecular reactions.
Proceedings of the 2010 International Conference on ComputerAided Design, 2010
Underdetermined blind source separation based on Continuous Density Hidden Markov Models.
Proceedings of the IEEE International Conference on Acoustics, 2010
Novel Variable length Teager Energy Based features for person recognition from their hum.
Proceedings of the IEEE International Conference on Acoustics, 2010
Seizure prediction with spectral power of time/spacedifferential EEG signals using costsensitive support vector machine.
Proceedings of the IEEE International Conference on Acoustics, 2010
Signal Flow Graphs and Data Flow Graphs.
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
Low Complexity Decoder Architecture for LowDensity ParityCheck Codes.
Signal Processing Systems, 2009
PulsedOFDM Modulation for Ultrawideband Communications.
IEEE Trans. Vehicular Technology, 2009
A lowcomplexity hybrid LDPC code encoder for IEEE 802.3an (10GBaseT) ethernet.
IEEE Trans. Signal Processing, 2009
Probabilistic Spherical Detection and VLSI Implementation for MultipleAntenna Systems.
IEEE Trans. on Circuits and Systems, 2009
LowLatency LowComplexity Architectures for Viterbi Decoders.
IEEE Trans. on Circuits and Systems, 2009
A Pipelined FFT Architecture for RealValued Signals.
IEEE Trans. on Circuits and Systems, 2009
Novel FEXT Cancellation and Equalization for High Speed Ethernet Transmission.
IEEE Trans. on Circuits and Systems, 2009
Sparse severe error removal in OFDM demodulators for erasure channels.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Variable Length Teager Energy Based Mel Cepstral Features for Identification of Twins.
Proceedings of the Pattern Recognition and Machine Intelligence, 2009
Noise Reduction for Lowpower Broadband Filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Lowpower Frequency Selective Filtering.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Synthesizing sequential registerbased computation with biochemistry.
Proceedings of the 2009 International Conference on ComputerAided Design, 2009
2008
HighSpeed VLSI Implementation of 2D Discrete Wavelet Transform.
IEEE Trans. Signal Processing, 2008
Design of Parallel TomlinsonHarashima Precoders.
IEEE Trans. on Circuits and Systems, 2008
Hardware Efficient LowLatency Architecture for High Throughput Rate Viterbi Decoders.
IEEE Trans. on Circuits and Systems, 2008
LowComplexity Echo and NEXT Cancellers for HighSpeed Ethernet Transceivers.
IEEE Trans. on Circuits and Systems, 2008
Minimal complexity lowlatency architectures for Viterbi decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Further cost reduction of adaptive echo and next cancellers for highspeed Ethernet transceivers.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Area efficient controller design of barrel shifters for reconfigurable LDPC decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Nonuniformly quantized minsum decoder architecture for lowdensity paritycheck codes.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Fast composite field Sbox architectures for advanced encryption standard.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Pipelined Parallel DecisionFeedback Decoders for HighSpeed Ethernet Over Copper.
IEEE Trans. Signal Processing, 2007
HighSpeed Architecture Design of TomlinsonHarashima Precoders.
IEEE Trans. on Circuits and Systems, 2007
Design of a SampleRate Converter From CD to DAT Using Fractional Delay Allpass Filter.
IEEE Trans. on Circuits and Systems, 2007
HighThroughput VLSI Architecture for FFT Computation.
IEEE Trans. on Circuits and Systems, 2007
LowCost Fast VLSI Algorithm for Discrete Fourier Transform.
IEEE Trans. on Circuits and Systems, 2007
Low Cost Parallel FIR Filter Structures With 2Stage Parallelism.
IEEE Trans. on Circuits and Systems, 2007
Parallel Architecture of List Sphere Decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Performance of Quantized MinSum Decoding Algorithms for Irregular LDPC Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Efficient HighlyParallel Decoder Architecture for QuasiCyclic LowDensity ParityCheck Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Fast Computation of MIMO Equalizers and Cancellers in 1OgbaseT Channels.
Proceedings of the IEEE International Conference on Acoustics, 2007
2006
Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper.
VLSI Signal Processing, 2006
Models for Architectural Power and Power Grid Noise Analysis on Data Bus.
VLSI Signal Processing, 2006
Hardware efficient fast computation of the discrete fourier transform.
VLSI Signal Processing, 2006
Hardware Efficient Fast Computation of the Discrete Fourier Transform.
VLSI Signal Processing, 2006
On the Optimum Constructions of Composite Field for the AES Algorithm.
IEEE Trans. on Circuits and Systems, 2006
HighSpeed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming.
IEEE Trans. on Circuits and Systems, 2006
Low Complexity List Updating Circuits for List Sphere Decoders.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Low Complexity Implementations of SumProduct Algorithm for Decoding LowDensity ParityCheck Codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Low complexity iterative joint detection, decoding, and channel estimation for wireless MIMO system.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Adaptive Tap Management in MultiGigabit Echo & Next Cancellers.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Low complexity block turbo equalization.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Faster elliptic curve point multiplication based on a novel greedy base2, 3 method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Study of Early Stopping Criteria for Turbo Decoding and Their Applications in WCDMA Systems.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Probabilistic List Sphere Decoding for LDPCCoded MIMOOFDM Systems.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Implementation Issues of a List Sphere Decoder.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
MIMO Equalization and Cancellation for 10GbaseT^{1}.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Low Complexity Design of High Speed Parallel Decision Feedback Equalizers.
Proceedings of the 2006 IEEE International Conference on ApplicationSpecific Systems, 2006
2005
Guest Editorial.
VLSI Signal Processing, 2005
On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes.
VLSI Signal Processing, 2005
Fast factorization architecture in softdecision ReedSolomon decoding.
IEEE Trans. VLSI Syst., 2005
Design of multigigabit multiplexerloopbased decision feedback equalizers.
IEEE Trans. VLSI Syst., 2005
From the Desk of the EditorinChief.
IEEE Trans. on Circuits and Systems, 2005
A novel systolic array structure for DCT.
IEEE Trans. on Circuits and Systems, 2005
VLSI architectures for stereoscopic video disparity matching and object extraction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Quasicyclic lowdensity paritycheck coded multibandOFDM UWB systems.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Pipelining TomlinsonHarashima precoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Further complexity reduction of parallel FIR filters.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Viterbi decoder for highspeed ultrawideband communication systems.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Pipelined parallel decision feedback decoders (PDFDs) for high speed Ethernet over copper.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
A new reconfigurable bitserial systolic divider for GF(2^{m}) and GF(p).
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
Highspeed VLSI architectures for the AES algorithm.
IEEE Trans. VLSI Syst., 2004
Lowlatency architectures for highthroughput rate Viterbi decoders.
IEEE Trans. VLSI Syst., 2004
Design of lowerror fixedwidth modified booth multiplier.
IEEE Trans. VLSI Syst., 2004
Small area parallel Chien search architectures for long BCH codes.
IEEE Trans. VLSI Syst., 2004
Joint (3, k)regular LDPC code and decoder/encoder design.
IEEE Trans. Signal Processing, 2004
Pipelined CORDICbased statespace orthogonal recursive digital filters using matrix lookahead.
IEEE Trans. Signal Processing, 2004
A new approach for integration of minarea retiming and mindelay padding for simultaneously addressing shortpath and longpath constraints.
ACM Trans. Design Autom. Electr. Syst., 2004
On the better protection of shortframe turbo codes.
IEEE Trans. Communications, 2004
On The Performance/Complexity Tradeoff in Block Turbo Decoder Design.
IEEE Trans. Communications, 2004
An improved pipelined MSBfirst addcompare select unit structure for Viterbi decoders.
IEEE Trans. on Circuits and Systems, 2004
The Editor's Corner.
IEEE Trans. on Circuits and Systems, 2004
Overlapped message passing for quasicyclic lowdensity parity check codes.
IEEE Trans. on Circuits and Systems, 2004
Parallel Turbo decoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
High performance solution for interfering UWB piconets with reduced complexity sphere decoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Pulsed OFDM modulation for ultra wideband communications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Novel pipelining of MSBfirst addcompare select unit structure for Viterbi decoders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Hardware efficient fast parallel FIR filter structures based on iterated short convolution.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Reduced complexity sphere decoding and application to interfering IEEE 802.15.3a piconets.
Proceedings of IEEE International Conference on Communications, 2004
Design and implementation of multiband pulsedOFDM system for wireless personal area networks.
Proceedings of IEEE International Conference on Communications, 2004
Eliminating the fanout bottleneck in parallel long BCH encoders.
Proceedings of IEEE International Conference on Communications, 2004
Area efficient decoding of quasicyclic low density parity check codes.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Pipelining of parallel multiplexer loops and decision feedback equalizers.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Interleaved trellis coded modulation and decoding for 10 Gigabit Ethernet over copper.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Area efficient parallel decoder architecture for long BCH codes.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Highspeed architectures for parallel long BCH encoders.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
2003
DigitSerial ComplexNumber Multipliers on FPGAs.
VLSI Signal Processing, 2003
A Low Power Correlator for CDMA Wireless Systems.
VLSI Signal Processing, 2003
Relaxed AnnihilationReordering LookAhead QRDRLS Adaptive Filters.
VLSI Signal Processing, 2003
Synthesis of minimumarea folded architectures for rectangular multidimensional multirate DSP systems.
IEEE Trans. Signal Processing, 2003
High performance, high throughput turbo/SOVA decoder design.
IEEE Trans. Communications, 2003
An FPGA Implementation of (3, 6)Regular LowDensity ParityCheck Code Decoder.
EURASIP J. Adv. Sig. Proc., 2003
Editorial.
EURASIP J. Adv. Sig. Proc., 2003
Interleaved Convolutional Code and Its Viterbi Decoder Architecture.
EURASIP J. Adv. Sig. Proc., 2003
LowComplexity Decoding of Block TurboCoded System with Antenna Diversity.
EURASIP J. Adv. Sig. Proc., 2003
Highspeed tunable fractionaldelay allpass filter structure.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Efficient interleaver memory architectures for serial turbo decoding.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
An asynchronous samplerate converter from CD to DAT.
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
High throughput overlapped message passing for low density parity check codes.
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
2002
Evaluation of CORDIC Algorithms for FPGA Design.
VLSI Signal Processing, 2002
Energy Efficient Signaling in Deepsubmicron Technology.
VLSI Design, 2002
Areaefficient highspeed decoding schemes for turbo decoders.
IEEE Trans. VLSI Syst., 2002
Fast and exact transistor sizing based on iterative relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002
PCORDIC: A Precomputation Based Rotation CORDIC Algorithm.
EURASIP J. Adv. Sig. Proc., 2002
Frequency Spectrum Based LowArea LowPower Parallel FIR Filter Design.
EURASIP J. Adv. Sig. Proc., 2002
Design of low error CSD fixedwidth multiplier.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Highspeed addcompareselect units using locally selfresetting CMOS.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
High speed VLSI architecture design for block turbo decoder.
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
High speed algorithm and VLSI architecture design for decoding BCH product codes.
Proceedings of the IEEE International Conference on Acoustics, 2002
A very low complexity soft decoding of spacetime block codes.
Proceedings of the IEEE International Conference on Acoustics, 2002
On the highspeed VLSI implementation of errorsanderasures correcting reedsolomon decoders.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
2001
Finite Wordlength Analysis and Adaptive Decoding for Turbo/MAP Decoders.
VLSI Signal Processing, 2001
A Novel Lowpower Shared Division and Squareroot Architecture Using the GST Algorithm.
VLSI Design, 2001
A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms.
IEEE Trans. Signal Processing, 2001
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials.
IEEE Trans. Computers, 2001
Vector processing of wavelet coefficients for robust image denoising.
Image Vision Comput., 2001
Energy Efficient Signaling in Deep Submicron CMOS Technology.
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
On finite precision implementation of low density parity check codes decoder.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Custom VLSI design of efficient low latency and low power finite field multiplier for ReedSolomon codec.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Energy efficient signaling in DSM CMOS technology.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
A study on the performance, complexity tradeoffs of block turbo decoder design.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Areaefficient high speed decoding schemes for turbo/MAP decoders.
Proceedings of the IEEE International Conference on Acoustics, 2001
A study on the performance, power consumption tradeoffs of short frame turbo decoder design.
Proceedings of the IEEE International Conference on Acoustics, 2001
A class of efficientencoding generalized lowdensity paritycheck codes.
Proceedings of the IEEE International Conference on Acoustics, 2001
Models for power consumption and power grid noise due to datapath transition activity.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
A very low complexity block turbo decoder composed of extended Hamming codes.
Proceedings of the Global Telecommunications Conference, 2001
Highperformance, lowcomplexity decoding of generalized lowdensity paritycheck codes.
Proceedings of the Global Telecommunications Conference, 2001
2000
Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications.
VLSI Signal Processing, 2000
Hardware/software codesign of finite field datapath for lowenergy ReedSolomon codecs.
IEEE Trans. VLSI Syst., 2000
Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μrotations.
IEEE Trans. Signal Processing, 2000
Annihilationreordering lookahead pipelined CORDICbased RLS adaptive filters and their application to adaptive beamforming.
IEEE Trans. Signal Processing, 2000
Power Estimation of Digital Data Paths Using HEAT.
IEEE Design & Test of Computers, 2000
Efficient approaches to improving performance of VLSI SOVAbased turbo decoders.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
FPGAbased digitserial complex number multiplieraccumulator.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Decoding metrics and their applications in VLSI turbo decoders.
Proceedings of the IEEE International Conference on Acoustics, 2000
Explicit CookToom algorithm for linear convolution.
Proceedings of the IEEE International Conference on Acoustics, 2000
A novel multiply multiple accumulator component for low power PDSP design.
Proceedings of the IEEE International Conference on Acoustics, 2000
Hierarchical pipelining and folding of QRDRLS adaptive filters.
Proceedings of the IEEE International Conference on Acoustics, 2000
High throughput low energy FEC/ARQ technique for short frame turbo codes.
Proceedings of the IEEE International Conference on Acoustics, 2000
Reducing bus transition activity by limited weight coding with codeword slimming.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
A lowpower correlator.
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
MINFLOTRANSIT: mincost flow based transistor sizing tool.
Proceedings of the 37th Conference on Design Automation, 2000
Data transmission over a bus with peaklimited transition activity.
Proceedings of ASPDAC 2000, 2000
Synthesis of low power folded programmable coefficient FIR digital filters (short paper).
Proceedings of ASPDAC 2000, 2000
BlockUpdate Parallel Processing QRDRLS Algorithm for Throughput Improvement with Low Power Consumption.
Proceedings of the 12th IEEE International Conference on ApplicationSpecific Systems, 2000
PerformanceScalable Array Architectures for Modular Multiplication.
Proceedings of the 12th IEEE International Conference on ApplicationSpecific Systems, 2000
1999
A Radix 2 Shared Division/Square Root Algorithm and its VLSI Architecture.
VLSI Signal Processing, 1999
Lowenergy CSMT carry generators and binary adders.
IEEE Trans. VLSI Syst., 1999
Twodimensional retiming [VLSI design].
IEEE Trans. VLSI Syst., 1999
Multidimensional carrierless AM/PM systems for digital subscriber loops.
IEEE Trans. Communications, 1999
Low power synthesis of dual threshold voltage CMOS VLSI circuits.
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Areapowertime efficient pipelineinterleaved architectures for wave digital filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Lowcomplexity modified Mastrovito multipliers over finite fields GF(2M).
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Lowenergy software ReedSolomon codecs using specialized finite field datapath and divisionfree BerlekampMassey algorithm.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Multiple access over wireline channels using orthogonal signaling.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Parallel modular multiplication with application to VLSI RSA implementation.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Pipelined QR decomposition based multichannel least square lattice adaptive filter architectures.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Efficient Crosstalk Estimation.
Proceedings of the IEEE International Conference On Computer Design, 1999
A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations.
Proceedings of the IEEE International Conference On Computer Design, 1999
Marsh: minarea retiming with setup and hold constraints.
Proceedings of the 1999 IEEE/ACM International Conference on ComputerAided Design, 1999
Lowpower bitserial Viterbi decoder for next generation wideband CDMA systems.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
An unrestrictedly parallel scheme for ultrahighrate reprogrammable Huffman coding.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
Theoretical Analysis of WordLevel Switching Activity in the Presence of Glitching and Correlation.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLSVLSI '99), 1999
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages.
Proceedings of the 36th Conference on Design Automation, 1999
Low Power Gate Resizing of Combinational Circuits by BufferRedistribution.
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999
1998
Guest Editors' Introduction.
VLSI Signal Processing, 1998
Heuristic LoopBased Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.
VLSI Signal Processing, 1998
Efficient semisystolic architectures for finitefield arithmetic.
IEEE Trans. VLSI Syst., 1998
ILPbased costoptimal DSP synthesis with module selection and data format conversion.
IEEE Trans. VLSI Syst., 1998
Synthesis of folded pipelined architectures for multirate DSP algorithms.
IEEE Trans. VLSI Syst., 1998
New SvobodaTung Division.
IEEE Trans. Computers, 1998
Fast lowpower shared division and squareroot architecture.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Low power SRAM design using hierarchical divided bitline approach.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Highperformance digitserial complexnumber multiplieraccumulator.
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Synthesis of folded, pipelined architectures for multidimensional multirate systems.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Lowenergy heterogeneous digitserial ReedSolomon codecs.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Pipelined CORDIC based QRDMVDR adaptive beamforming.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1997
LowArea/Power Parallel FIR Digital Filter Implementations.
VLSI Signal Processing, 1997
Guest Editors' Introduction.
VLSI Signal Processing, 1997
A Generalized Technique for Register Counting and its Application to CostOptimal DSP Architecture Synthesis.
VLSI Signal Processing, 1997
Finiteprecision error analysis of QRDRLS and STARRLS adaptive filters.
IEEE Trans. Signal Processing, 1997
Radix 2 Division with OverRedundant Quotient Selection.
IEEE Trans. Computers, 1997
A WaveletDomain Algorithm for Denoising in the Presence of Noise Outliers.
Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997
Fast LowEnergy VLSI Binary Addition.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Design and Implementation of LowPower DigitSerial Multipliers.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Lowarea dual basis divider over GF(2^{M}).
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Pipelining of cordic based IIR digital filters.
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
1996
Lower bounds on memory requirements for statically scheduled DSP programs.
VLSI Signal Processing, 1996
Pipelined RLS adaptive filtering using scaled tangent rotations (STAR).
IEEE Trans. Signal Processing, 1996
Systematic analysis of bounds on power consumption in pipelined and nonpipelined multipliers.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
A hierarchical approach to transistorlevel power estimation of arithmetic units.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Efficient standard basis ReedSolomon encoder.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Twodimensional retiming with low memory requirements.
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Orderconfigurable programmable powerefficient FIR filters.
Proceedings of the 3rd International Conference on High Performance Computing, 1996
LoopList Scheduling for Heterogeneous Functional Units.
Proceedings of the 6th Great Lakes Symposium on VLSI (GLSVLSI '96), 1996
HEAT: Hierarchical Energy Analysis Tool.
Proceedings of the 33st Conference on Design Automation, 1996
Efficient Finite Field Serial/Parallel Multiplication.
Proceedings of the 1996 International Conference on ApplicationSpecific Systems, 1996
AreaEfficient Parallel FIR Digital Filter Implementations.
Proceedings of the 1996 International Conference on ApplicationSpecific Systems, 1996
1995
Resourceconstrained loop list scheduler for DSP algorithms.
VLSI Signal Processing, 1995
Highlevel algorithm and architecture transformations for DSP synthesis.
VLSI Signal Processing, 1995
Determining the minimum iteration period of an algorithm.
VLSI Signal Processing, 1995
Pipelined adaptive DFE architectures using relaxed lookahead.
IEEE Trans. Signal Processing, 1995
Highlevel DSP synthesis using concurrent transformations, scheduling, and allocation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1995
A Fast Radix4 Division Algorithm and Its Architecture.
IEEE Trans. Computers, 1995
A 16bit x 16bit 1.2 /spl mu/ CMOS multiplier with low latency vector merging.
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
LowPower FIR Digital Filter Architectures.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Two VLSI Design Advances in Arithmetic Coding.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Generalized Multiplication Free Arithmetic Codes.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Synthesis and Pipelining of Ladder Wave Digital Filters in Digital Domain.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
A floating point radix 2 shared division/square root chip.
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
A 100 MHz pipelined RLS adaptive filter.
Proceedings of the 1995 International Conference on Acoustics, 1995
Low latency standard basis GF(2^{m}) multiplier and squarer architectures.
Proceedings of the 1995 International Conference on Acoustics, 1995
1994
Pipelining of lattice IIR digital filters.
IEEE Trans. Signal Processing, 1994
Sequential and Parallel Neural Network Vector Quantizers.
IEEE Trans. Computers, 1994
Input compression and efficient VLSI architectures for rank order and stack filters.
Signal Processing, 1994
Calculation of Minimum Number of Registers in Arbitrary Life Time Chart.
Proceedings of the Seventh International Conference on VLSI Design, 1994
A Fast Radix4 Division Algorithm.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Calculation of Minimum Number of Registers in 2D Discrete Wavelet Transforms Using Lapped Block Processing.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Module selection and data format conversion for costoptimal DSP synthesis.
Proceedings of the 1994 IEEE/ACM International Conference on ComputerAided Design, 1994
Fixed and floating point error analysis of QRDRLS and STARRLS adaptive filters.
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994
Architectures for lattice structure based orthonormal discrete wavelet transforms.
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
VLSI architectures for discrete wavelet transforms.
IEEE Trans. VLSI Syst., 1993
A pipelined adaptive lattice filter architecture.
IEEE Trans. Signal Processing, 1993
Parallel adaptive decision feedback equalizers.
IEEE Trans. Signal Processing, 1993
Dataflow transformations for critical path time reduction in highlevel DSP synthesis.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1993
HighSpeed Arithmetic Coder/Decoder Architectures.
Proceedings of the Sixth SIAM Conference on Parallel Processing for Scientific Computing, 1993
Loop List Scheduler for DSP Algorithms under Resource Consraints.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A Pipelined Adaptive Differential Vector Quantizer for Lowpower Speech Coding Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Roundoff error analysis of the pipelined ADPCM coder.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
High Speed RLS Using Scaled Tangent Rotations (STAR).
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Folded VLSI Architectures for Discrete Wavelet Transforms.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
The scaled normalized lattice digital filter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A CTestable CarryFree Divider.
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Highspeed arithmetic coder/decoder architectures.
Proceedings of the IEEE International Conference on Acoustics, 1993
Block processing for rank order filtering using the rank order state machine architecture.
Proceedings of the IEEE International Conference on Acoustics, 1993
Combining neural networks and the wavelet transform for image compression.
Proceedings of the IEEE International Conference on Acoustics, 1993
Parallel processing architectures for rank order and stack filters.
Proceedings of the International Conference on ApplicationSpecific Array Processors, 1993
1992
Video data format converters using minimum number of registers.
IEEE Trans. Circuits Syst. Video Techn., 1992
1991
Finite word effects in pipelined recursive filters.
IEEE Trans. Signal Processing, 1991
Pipelining in dynamic programming architectures.
IEEE Trans. Signal Processing, 1991
Static RateOptimal Scheduling of Iterative DataFlow Programs via Optimum Unfolding.
IEEE Trans. Computers, 1991
HighSpeed VLSI Arithmetic Processor Architectures Using Hybrid Number Representation.
Proceedings of the Proceedings 1991 IEEE International Conference on Computer Design: VLSI in Computer & Processors, 1991
1990
Automatic generation of control circuits in pipelined DSP architectures.
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
1989
Pipeline interleaving and parallelism in recursive digital filters. II. Pipelined incremental block filtering.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1989
Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered lookahead and decomposition.
IEEE Trans. Acoustics, Speech, and Signal Processing, 1989
Distributed Scheduling of Broadcasts in a Radio Network.
Proceedings of the Proceedings IEEE INFOCOM '89, 1989
FullyStatic RateOptimal Scheduling of Iterative DataFlow Programs via Optimum Unfolding.
Proceedings of the International Conference on Parallel Processing, 1989