Keshab K. Parhi
According to our database^{1},
Keshab K. Parhi
authored at least 437 papers
between 1987 and 2020.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 1996, "For contributions to the fields of VLSI digital signal processing architectures, design methodologies and tools.".
Timeline
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Online presence:

on orcid.org

on ee.umn.edu
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Bibliography
2020
M3U: Minimum Mean Minimum Uncertainty Feature Selection for Multiclass Classification.
J. Signal Process. Syst., 2020
IEEE Trans. Inf. Forensics Secur., 2020
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
IEEE Trans. Biomed. Circuits Syst., 2020
Probabilistic Hardware Trojan Attacks on Multiple Layers of Reconfigurable Network Infrastructure.
J. Hardw. Syst. Secur., 2020
An Inference and Learning Engine for Spiking Neural Networks in Computational RAM (CRAM).
CoRR, 2020
CoRR, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
2019
Architecture Optimization and Performance Comparison of NonceMisuseResistant Authenticated Encryption Algorithms.
IEEE Trans. Very Large Scale Integr. Syst., 2019
RETOUCH: The Retinal OCT Fluid Detection and Segmentation Benchmark and Challenge.
IEEE Trans. Medical Imaging, 2019
IEEE Trans. Knowl. Data Eng., 2019
IEEE Trans. Emerg. Top. Comput., 2019
Discriminative Ratio of Spectral Power and Relative Power Features Derived via FrequencyDomain Model Ratio With Application to Seizure Prediction.
IEEE Trans. Biomed. Circuits Syst., 2019
ProTro: A Probabilistic Counter Based Hardware Trojan Attack on FPGA Based MACSec Enabled Ethernet Switch.
Proceedings of the Security, Privacy, and Applied Cryptography Engineering, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Effect of Loop Positions on Reliability and Attack Resistance of FeedForward PUFs.
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019
Proceedings of the 2019 on Great Lakes Symposium on VLSI, 2019
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
Proceedings of the 41st Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2019
Computing Radial Basis Function Support Vector Machine using DNA via Fractional Coding.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019
A 3.01 mm<sup>2</sup> 65.38Gb/s Stochastic LDPC Decoder for IEEE 802.3an in 65 nm.
Proceedings of the IEEE Asian SolidState Circuits Conference, 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
Converting Unstable Challenges to Stable in MUXbased Physical Unclonable Functions by BitFlipping.
Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019
2018
J. Signal Process. Syst., 2018
J. Signal Process. Syst., 2018
KeyBased Dynamic Functional Obfuscation of Integrated Circuits Using Sequentially Triggered ModeBased Design.
IEEE Trans. Inf. Forensics Secur., 2018
Stochastic Logic Implementations of Polynomials With All Positive Coefficients by Expansion Methods.
IEEE Trans. Circuits Syst. II Express Briefs, 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
Fully Automated Segmentation of Fluid/Cyst Regions in Optical Coherence Tomography Images With Diabetic Macular Edema Using Neutrosophic Sets and Graph Algorithms.
IEEE Trans. Biomed. Eng., 2018
IncrementalPrecision Based Feature Computation and MultiLevel Classification for LowEnergy InternetofThings.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2018
Proceedings of the 51st Annual IEEE/ACM International Symposium on Microarchitecture, 2018
A Physical Unclonable Function based on Capacitor Mismatch in a ChargeRedistribution SARADC.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Predicting SoftResponse of MUX PUFs via Logistic Regression of Total Delay Difference.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
LowEnergy Architectures of Linear Classifiers for IoT Applications using Incremental Precision and MultiLevel Classification.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
OCT Fluid Segmentation using Graph Shortest Path and Convolutional Neural Network<sup>*</sup>.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Classifying Treated vs. Untreated MDD Adolescents from Anatomical Connectivity using Nonlinear SVM.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Anatomical Biomarkers for Adolescent Major Depressive Disorder from Diffusion Weighted Imaging using SVM Classifier.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Biomarkers for Adolescent MDD from Anatomical Connectivity and Network Topology Using Diffusion MRI.
Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018
Constrained Tensor Decomposition Optimization With Applications To Fmri Data Analysis.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
Classifying Adolescent Major Depressive Disorder using Linear SVM with Anatomical Features from Diffusion Weighted Imaging.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
Altered Structural Connection Between Hippocampus and Insula in Adolescent Major Depressive Disorder using DTI.
Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018
2017
LLRBased SuccessiveCancellation List Decoder for Polar Codes With Multibit Decision.
IEEE Trans. Circuits Syst. II Express Briefs, 2017
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
ACM J. Emerg. Technol. Comput. Syst., 2017
EURASIP J. Adv. Signal Process., 2017
Predicting hard and softresponses and identifying stable challenges of MUX PUFs using ANNs.
Proceedings of the IEEE 60th International Midwest Symposium on Circuits and Systems, 2017
A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function.
Proceedings of the 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Hierarchical functional obfuscation of integratec circuits using a modebased approach.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
FPGA implementation and comparison of AESGCM and Deoxys authenticated encryption schemes.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Extraction of common task signals and spatial maps from group fMRI using a PARAFACbased tensor decomposition technique.
Proceedings of the 2017 IEEE International Conference on Acoustics, 2017
Computing Polynomials with Positive Coefficients using Stochastic Logic by DoubleNAND Expansion.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017
Secure and Reliable XOR Arbiter PUF Design: An Experimental Study based on 1 Trillion Challenge Response Pair Measurements.
Proceedings of the 54th Annual Design Automation Conference, 2017
A DRAM based physical unclonable function capable of generating >10<sup>32</sup> Challenge Response Pairs per 1Kbit array for secure chip authentication.
Proceedings of the 2017 IEEE Custom Integrated Circuits Conference, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
Performance comparison of AESGCMSIV and AESGCM algorithms for authenticated encryption on FPGA platforms.
Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017
2016
IEEE Trans. Signal Process., 2016
IEEE J. Biomed. Health Informatics, 2016
LowComplexity Seizure Prediction From iEEG/sEEG Using Spectral Power and Ratios of Spectral Power.
IEEE Trans. Biomed. Circuits Syst., 2016
Beat Frequency DetectorBased HighSpeed True Random Number Generators: Statistical Modeling and Analysis.
ACM J. Emerg. Technol. Comput. Syst., 2016
LLRbased SuccessiveCancellation List Decoder for Polar Codes with Multibit Decision.
CoRR, 2016
CoRR, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Proceedings of the 2016 IEEE International Workshop on Signal Processing Systems, 2016
Soft Response Generation and Thresholding Strategies for Linear and FeedForward MUX PUFs.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
Proceedings of the Third Workshop on Cryptography and Security in Computing Systems, 2016
Proceedings of the 26th edition on Great Lakes Symposium on VLSI, 2016
Proceedings of the 2016 IEEE Global Communications Conference, 2016
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Automated detection of neovascularization for proliferative diabetic retinopathy screening.
Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016
Seizure prediction using longterm fragmented intracranial canine and human EEG recordings.
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016
2015
LowLatency SuccessiveCancellation List Decoders for Polar Codes With Multibit Decision.
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Very Large Scale Integr. Syst., 2015
IEEE Trans. Mol. Biol. Multi Scale Commun., 2015
Blood Vessel Segmentation of Fundus Images by Major Vessel Extraction and Subimage Classification.
IEEE J. Biomed. Health Informatics, 2015
IEEE Trans. Biomed. Eng., 2015
Early Seizure Detection Using Neuronal Potential Similarity: A Generalized LowComplexity and Robust Measure.
Int. J. Neural Syst., 2015
Proceedings of the Medical Imaging 2015: Image Processing, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Faulttolerant ripplecarry binary adder using partial triple modular redundancy (PTMR).
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Proceedings of the 2015 IEEE International Conference on Digital Signal Processing, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Proceedings of the 2015 IEEE International Conference on Acoustics, 2015
Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015
Seizure detection using regression tree based feature selection and polynomial SVM classification.
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Proceedings of the 37th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
Proceedings of the 49th Asilomar Conference on Signals, Systems and Computers, 2015
2014
J. Signal Process. Syst., 2014
Early Stopping Criteria for EnergyEfficient LowLatency BeliefPropagation Polar Code Decoders.
IEEE Trans. Signal Process., 2014
IEEE J. Biomed. Health Informatics, 2014
IEEE Trans. Circuits Syst. II Express Briefs, 2014
LowLatency SuccessiveCancellation Polar Decoder Architectures Using 2Bit Decoding.
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Circuits Syst. I Regul. Pap., 2014
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2014
LowLatency SuccessiveCancellation List Decoders for Polar Codes with Multibit Decision.
CoRR, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA  May 21, 2014
Seizure detection using wavelet decomposition of the prediction error signal from a single channel of intracranial EEG.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
Classification of borderline personality disorder based on spectral power of restingstate fMRI.
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014
True Random Number Generator circuits based on single and multiphase beat frequency detection.
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
Proceedings of the 48th Asilomar Conference on Signals, Systems and Computers, 2014
2013
Proceedings of the Handbook of Signal Processing Systems, 2013
Design and Optimization of Multiplierless FIR Filters Using SubThreshold Circuits.
J. Signal Process. Syst., 2013
IEEE Trans. Very Large Scale Integr. Syst., 2013
LowLatency Sequential and Overlapped Architectures for Successive Cancellation Polar Decoder.
IEEE Trans. Signal Process., 2013
Pipelined Architectures for RealValued FFT and HermitianSymmetric IFFT With Real Datapaths.
IEEE Trans. Circuits Syst. II Express Briefs, 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
FFT Architectures for RealValued Signals Based on Radix2<sup>3</sup> and Radix2<sup>4</sup> Algorithms.
IEEE Trans. Circuits Syst. I Regul. Pap., 2013
IEEE Trans. Circuits Syst. II Express Briefs, 2013
Optimized joint timing synchronization and channel estimation for communications systems with multiple transmit antennas.
EURASIP J. Adv. Signal Process., 2013
Performance evaluation of variable transmission rate OFDM systems via network source coding.
EURASIP J. Adv. Signal Process., 2013
Semiblind frequencydomain timing synchronization and channel estimation for OFDM systems.
EURASIP J. Adv. Signal Process., 2013
Proceedings of the IEEE/ACM International Conference on ComputerAided Design, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Proceedings of the IEEE International Conference on Acoustics, 2013
Automated localization of cysts in diabetic macular edema using optical coherence tomography images.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Seizure prediction with bipolar spectral power features using Adaboost and SVM classifiers.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
Proceedings of the 2013 Asilomar Conference on Signals, 2013
2012
IEEE Wirel. Commun. Lett., 2012
IEEE Trans. Very Large Scale Integr. Syst., 2012
IEEE Trans. Circuits Syst. I Regul. Pap., 2012
Static and dynamic information derived from source and system features for person recognition from humming.
Int. J. Speech Technol., 2012
IEEE Des. Test Comput., 2012
Variable data rate (VDR) network congestion control (NCC) applied to voice/audio communication.
Comput. Networks, 2012
Proceedings of IEEE International Conference on Communications, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Proceedings of the Great Lakes Symposium on VLSI 2012, 2012
Selection of abnormal neural oscillation patterns associated with sentencelevel language disorder in Schizophrenia.
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Reducing the number of features for seizure prediction of spectral power in intracranial EEG.
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012
2011
IEEE Trans. Signal Process., 2011
IEEE Trans. Circuits Syst. II Express Briefs, 2011
IEEE J. Emerg. Sel. Topics Circuits Syst., 2011
CoRR, 2011
CoRR, 2011
Combining Evidence from Spectral and SourceLike Features for Person Recognition from Humming.
Proceedings of the INTERSPEECH 2011, 2011
Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
Fast Reconfigurable Elliptic Curve Cryptography Acceleration for <i>GF</i>(2<sup><i>m</i></sup>) on 32 bit Processors.
J. Signal Process. Syst., 2010
IEEE Trans. Very Large Scale Integr. Syst., 2010
Computation Error Analysis in Digital Signal Processing Systems With Overscaled Supply Voltage.
IEEE Trans. Very Large Scale Integr. Syst., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
Proceedings of the Biocomputing 2010: Proceedings of the Pacific Symposium, 2010
Proceedings of the 2010 International Conference on ComputerAided Design, 2010
Underdetermined blind source separation based on Continuous Density Hidden Markov Models.
Proceedings of the IEEE International Conference on Acoustics, 2010
Novel Variable length Teager Energy Based features for person recognition from their hum.
Proceedings of the IEEE International Conference on Acoustics, 2010
Seizure prediction with spectral power of time/spacedifferential EEG signals using costsensitive support vector machine.
Proceedings of the IEEE International Conference on Acoustics, 2010
Proceedings of the Handbook of Signal Processing Systems, 2010
2009
J. Signal Process. Syst., 2009
IEEE Trans. Veh. Technol., 2009
IEEE Trans. Signal Process., 2009
Probabilistic Spherical Detection and VLSI Implementation for MultipleAntenna Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
IEEE Trans. Circuits Syst. I Regul. Pap., 2009
Proceedings of the IEEE Workshop on Signal Processing Systems, 2009
Variable Length Teager Energy Based Mel Cepstral Features for Identification of Twins.
Proceedings of the Pattern Recognition and Machine Intelligence, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
Proceedings of the 2009 International Conference on ComputerAided Design, 2009
2008
IEEE Trans. Signal Process., 2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
Hardware Efficient LowLatency Architecture for High Throughput Rate Viterbi Decoders.
IEEE Trans. Circuits Syst. II Express Briefs, 2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Further cost reduction of adaptive echo and next cancellers for highspeed Ethernet transceivers.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2008
Area efficient controller design of barrel shifters for reconfigurable LDPC decoders.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Nonuniformly quantized minsum decoder architecture for lowdensity paritycheck codes.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Pipelined Parallel DecisionFeedback Decoders for HighSpeed Ethernet Over Copper.
IEEE Trans. Signal Process., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Design of a SampleRate Converter From CD to DAT Using Fractional Delay Allpass Filter.
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
IEEE Trans. Circuits Syst. I Regul. Pap., 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Efficient HighlyParallel Decoder Architecture for QuasiCyclic LowDensity ParityCheck Codes.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the IEEE International Conference on Acoustics, 2007
2006
Interleaved Trellis Coded Modulation and Decoder Optimizations for 10 Gigabit Ethernet over Copper.
J. VLSI Signal Process., 2006
J. VLSI Signal Process., 2006
J. VLSI Signal Process., 2006
IEEE Trans. Signal Process., 2006
IEEE Trans. Signal Process., 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
HighSpeed Parallel CRC Implementation Based on Unfolding, Pipelining, and Retiming.
IEEE Trans. Circuits Syst. II Express Briefs, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Low Complexity Implementations of SumProduct Algorithm for Decoding LowDensity ParityCheck Codes.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Low complexity iterative joint detection, decoding, and channel estimation for wireless MIMO system.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the IEEE Workshop on Signal Processing Systems, 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Faster elliptic curve point multiplication based on a novel greedy base2, 3 method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Study of Early Stopping Criteria for Turbo Decoding and Their Applications in WCDMA Systems.
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 2006 IEEE International Conference on Acoustics Speech and Signal Processing, 2006
Proceedings of the 2006 IEEE International Conference on ApplicationSpecific Systems, 2006
2005
J. VLSI Signal Process., 2005
On the Performance and Implementation Issues of Interleaved Single Parity Check Turbo Product Codes.
J. VLSI Signal Process., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
VLSI architectures for stereoscopic video disparity matching and object extraction.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Pipelined parallel decision feedback decoders (PDFDs) for high speed Ethernet over copper.
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
Proceedings of the 2005 IEEE International Conference on Acoustics, 2005
2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Very Large Scale Integr. Syst., 2004
Design of lowerror fixedwidth modified booth multiplier.
IEEE Trans. Very Large Scale Integr. Syst., 2004
Small area parallel Chien search architectures for long BCH codes.
IEEE Trans. Very Large Scale Integr. Syst., 2004
IEEE Trans. Signal Process., 2004
Pipelined CORDICbased statespace orthogonal recursive digital filters using matrix lookahead.
IEEE Trans. Signal Process., 2004
A new approach for integration of minarea retiming and mindelay padding for simultaneously addressing shortpath and longpath constraints.
ACM Trans. Design Autom. Electr. Syst., 2004
IEEE Trans. Commun., 2004
IEEE Trans. Commun., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
An improved pipelined MSBfirst addcompare select unit structure for Viterbi decoders.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Hardware efficient fast parallel FIR filter structures based on iterated short convolution.
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
IEEE Trans. Circuits Syst. I Regul. Pap., 2004
Parallel Turbo decoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
High performance solution for interfering UWB piconets with reduced complexity sphere decoding.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Pulsed OFDM modulation for ultra wideband communications.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Novel pipelining of MSBfirst addcompare select unit structure for Viterbi decoders.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Reduced complexity sphere decoding and application to interfering IEEE 802.15.3a piconets.
Proceedings of IEEE International Conference on Communications, 2004
Design and implementation of multiband pulsedOFDM system for wireless personal area networks.
Proceedings of IEEE International Conference on Communications, 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Interleaved trellis coded modulation and decoding for 10 Gigabit Ethernet over copper.
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
Proceedings of the 2004 IEEE International Conference on Acoustics, 2004
2003
J. VLSI Signal Process., 2003
J. VLSI Signal Process., 2003
J. VLSI Signal Process., 2003
Synthesis of minimumarea folded architectures for rectangular multidimensional multirate DSP systems.
IEEE Trans. Signal Process., 2003
IEEE Trans. Commun., 2003
EURASIP J. Adv. Signal Process., 2003
EURASIP J. Adv. Signal Process., 2003
EURASIP J. Adv. Signal Process., 2003
EURASIP J. Adv. Signal Process., 2003
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
Proceedings of the 2003 IEEE International Conference on Acoustics, 2003
Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, 2003
2002
J. VLSI Signal Process., 2002
J. VLSI Signal Process., 2002
VLSI Design, 2002
IEEE Trans. Very Large Scale Integr. Syst., 2002
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002
EURASIP J. Adv. Signal Process., 2002
EURASIP J. Adv. Signal Process., 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the 2002 International Symposium on Circuits and Systems, 2002
Proceedings of the IEEE International Conference on Acoustics, 2002
Proceedings of the IEEE International Conference on Acoustics, 2002
On the highspeed VLSI implementation of errorsanderasures correcting reedsolomon decoders.
Proceedings of the 12th ACM Great Lakes Symposium on VLSI 2002, 2002
2001
J. VLSI Signal Process., 2001
A Novel Lowpower Shared Division and Squareroot Architecture Using the GST Algorithm.
VLSI Design, 2001
A unified algebraic transformation approach for parallel recursive and adaptive filtering and SVD algorithms.
IEEE Trans. Signal Process., 2001
Systematic Design of Original and Modified Mastrovito Multipliers for General Irreducible Polynomials.
IEEE Trans. Computers, 2001
Image Vis. Comput., 2001
Proceedings of the 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Custom VLSI design of efficient low latency and low power finite field multiplier for ReedSolomon codec.
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
A study on the performance, power consumption tradeoffs of short frame turbo decoder design.
Proceedings of the IEEE International Conference on Acoustics, 2001
Proceedings of the IEEE International Conference on Acoustics, 2001
Models for power consumption and power grid noise due to datapath transition activity.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
Proceedings of the Global Telecommunications Conference, 2001
Highperformance, lowcomplexity decoding of generalized lowdensity paritycheck codes.
Proceedings of the Global Telecommunications Conference, 2001
2000
Power Efficient Folding of Pipelined LMS Adaptive Filters with Applications to Wireline Digital Communications.
J. VLSI Signal Process., 2000
Hardware/software codesign of finite field datapath for lowenergy ReedSolomon codecs.
IEEE Trans. Very Large Scale Integr. Syst., 2000
Theoretical analysis of wordlevel switching activity in the presence of glitching and correlation.
IEEE Trans. Very Large Scale Integr. Syst., 2000
Efficient implementations of pipelined CORDIC based IIR digital filters using fast orthonormal μrotations.
IEEE Trans. Signal Process., 2000
Annihilationreordering lookahead pipelined CORDICbased RLS adaptive filters and their application to adaptive beamforming.
IEEE Trans. Signal Process., 2000
IEEE Des. Test Comput., 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the IEEE International Conference on Acoustics, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
Proceedings of the 10th ACM Great Lakes Symposium on VLSI 2000, 2000
Proceedings of the 37th Conference on Design Automation, 2000
Proceedings of ASPDAC 2000, 2000
Synthesis of low power folded programmable coefficient FIR digital filters (short paper).
Proceedings of ASPDAC 2000, 2000
BlockUpdate Parallel Processing QRDRLS Algorithm for Throughput Improvement with Low Power Consumption.
Proceedings of the 12th IEEE International Conference on ApplicationSpecific Systems, 2000
1999
J. VLSI Signal Process., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Very Large Scale Integr. Syst., 1999
IEEE Trans. Commun., 1999
Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999
Areapowertime efficient pipelineinterleaved architectures for wave digital filters.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Lowenergy software ReedSolomon codecs using specialized finite field datapath and divisionfree BerlekampMassey algorithm.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Derivation of parallel and pipelined orthogonal filter architectures via algorithm transformations.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Pipelined QR decomposition based multichannel least square lattice adaptive filter architectures.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
A Unified Method for Iterative Computation of Modular Multiplication and Reduction Operations.
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 1999 IEEE/ACM International Conference on ComputerAided Design, 1999
Proceedings of the 1999 IEEE International Conference on Communications: Global Convergence Through Communications, 1999
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
An unrestrictedly parallel scheme for ultrahighrate reprogrammable Huffman coding.
Proceedings of the 1999 IEEE International Conference on Acoustics, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 18th Conference on Advanced Research in VLSI (ARVLSI '99), 1999
1998
J. VLSI Signal Process., 1998
Heuristic LoopBased Scheduling and Allocation for DSP Synthesis with Heterogeneous Functional Units.
J. VLSI Signal Process., 1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
ILPbased costoptimal DSP synthesis with module selection and data format conversion.
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Very Large Scale Integr. Syst., 1998
IEEE Trans. Computers, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
Synthesis of folded, pipelined architectures for multidimensional multirate systems.
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
Proceedings of the 1998 IEEE International Conference on Acoustics, 1998
1997
J. VLSI Signal Process., 1997
J. VLSI Signal Process., 1997
A Generalized Technique for Register Counting and its Application to CostOptimal DSP Architecture Synthesis.
J. VLSI Signal Process., 1997
IEEE Trans. Signal Process., 1997
IEEE Trans. Commun., 1997
IEEE Trans. Computers, 1997
Proceedings of the Proceedings 1997 International Conference on Image Processing, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
Proceedings of the 1997 IEEE International Conference on Acoustics, 1997
1996
J. VLSI Signal Process., 1996
IEEE Trans. Signal Process., 1996
Systematic analysis of bounds on power consumption in pipelined and nonpipelined multipliers.
Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Proceedings of the 1996 IEEE International Conference on Acoustics, 1996
Proceedings of the 3rd International Conference on High Performance Computing, 1996
Proceedings of the 6th Great Lakes Symposium on VLSI (GLSVLSI '96), 1996
Proceedings of the 33st Conference on Design Automation, 1996
Proceedings of the 1996 International Conference on ApplicationSpecific Systems, 1996
Proceedings of the 1996 International Conference on ApplicationSpecific Systems, 1996
1995
J. VLSI Signal Process., 1995
J. VLSI Signal Process., 1995
J. VLSI Signal Process., 1995
IEEE Trans. Signal Process., 1995
Highlevel DSP synthesis using concurrent transformations, scheduling, and allocation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995
IEEE Trans. Computers, 1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
Proceedings of the 1995 International Conference on Acoustics, 1995
Low latency standard basis GF(2<sup>m</sup>) multiplier and squarer architectures.
Proceedings of the 1995 International Conference on Acoustics, 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
IEEE Trans. Signal Process., 1994
IEEE Trans. Signal Process., 1994
IEEE Trans. Computers, 1994
Input compression and efficient VLSI architectures for rank order and stack filters.
Signal Process., 1994
Proceedings of the Seventh International Conference on VLSI Design, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Calculation of Minimum Number of Registers in 2D Discrete Wavelet Transforms Using Lapped Block Processing.
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
Proceedings of the 1994 IEEE/ACM International Conference on ComputerAided Design, 1994
Proceedings of ICASSP '94: IEEE International Conference on Acoustics, 1994
Architectures for lattice structure based orthonormal discrete wavelet transforms.
Proceedings of the International Conference on Application Specific Array Processors, 1994
1993
IEEE Trans. Very Large Scale Integr. Syst., 1993
IEEE Trans. Signal Process., 1993
IEEE Trans. Signal Process., 1993
Dataflow transformations for critical path time reduction in highlevel DSP synthesis.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993
Loop List Scheduler for DSP Algorithms under Resource Consraints.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
A Pipelined Adaptive Differential Vector Quantizer for Lowpower Speech Coding Applications.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Roundoff error analysis of the pipelined ADPCM coder.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
High Speed RLS Using Scaled Tangent Rotations (STAR).
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Folded VLSI Architectures for Discrete Wavelet Transforms.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
The scaled normalized lattice digital filter.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the IEEE International Conference on Acoustics, 1993
Block processing for rank order filtering using the rank order state machine architecture.
Proceedings of the IEEE International Conference on Acoustics, 1993
Proceedings of the IEEE International Conference on Acoustics, 1993
1992
Highspeed VLSI arithmetic processor architectures using hybrid number representation.
J. VLSI Signal Process., 1992
IEEE Trans. Circuits Syst. Video Technol., 1992
Proceedings of the 1992 IEEE International Conference on Acoustics, 1992
1991
IEEE Trans. Signal Process., 1991
IEEE Trans. Signal Process., 1991
Static RateOptimal Scheduling of Iterative DataFlow Programs via Optimum Unfolding.
IEEE Trans. Computers, 1991
Neural network vector quantizer design using sequential and parallel learning techniques.
Proceedings of the 1991 International Conference on Acoustics, 1991
Proceedings of the 1991 International Conference on Acoustics, 1991
Proceedings of the 1991 International Conference on Acoustics, 1991
1990
Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990
Proceedings of the 1990 International Conference on Acoustics, 1990
Proceedings of the 1990 International Conference on Acoustics, 1990
Proceedings of the Application Specific Array Processors, 1990
1989
Pipeline interleaving and parallelism in recursive digital filters. II. Pipelined incremental block filtering.
IEEE Trans. Acoust. Speech Signal Process., 1989
Pipeline interleaving and parallelism in recursive digital filters. I. Pipelining using scattered lookahead and decomposition.
IEEE Trans. Acoust. Speech Signal Process., 1989
Proceedings of the Proceedings IEEE INFOCOM '89, 1989
FullyStatic RateOptimal Scheduling of Iterative DataFlow Programs via Optimum Unfolding.
Proceedings of the International Conference on Parallel Processing, 1989
1988
Pipelined VLSI recursive filter architectures using scattered lookahead and decomposition.
Proceedings of the IEEE International Conference on Acoustics, 1988
1987
Proceedings of the IEEE International Conference on Acoustics, 1987