Hsi-Che Tseng

According to our database, Hsi-Che Tseng authored at least 5 papers between 2009 and 2014.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2014

A high-performance VLSI architecture for variable block size motion estimation.

Hsin-Chou Chi, Han-Sheng Liu, Hsi-Che Tseng

Proceedings of the IEEE 3rd Global Conference on Consumer Electronics, 2014

2013

Reconfigurable VLSI digital filters for tolerating multiple timing errors.

Hsin-Chou Chi, Hsi-Che Tseng, Chia-Wei Jeng

Proceedings of the IEEE 2nd Global Conference on Consumer Electronics, 2013

2011

Efficient diagnosable design of the IEEE P1500 architecture for SoC testing.

Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang

Proceedings of the 2nd IEEE International Conference on Networked Embedded Systems for Enterprise Applications, 2011

Design of timing-error-resilient systolic arrays for matrix multiplication.

Hsin-Chou Chi, Hsi-Che Tseng, Kun-Lin Tsai

Proceedings of the International SoC Design Conference, 2011

2009

Efficient diagnosis of scan chains with single stuck-at faults.

Hsin-Chou Chi, Hsi-Che Tseng, Chih-Ling Yang

Proceedings of the 43rd Annual Conference on Information Sciences and Systems, 2009