Hsinwei Chou

According to our database, Hsinwei Chou authored at least 2 papers between 2005 and 2015.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2015

Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States.

Clayton B. McDonald, Hsinwei Chou, Vijay Durairaj, Pey-Chang Kent Lin

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2015

2005

Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation.

Hsinwei Chou, Yu-Hao Wang, Charlie Chung-Ping Chen

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005