Charlie Chung-Ping Chen

According to our database1, Charlie Chung-Ping Chen authored at least 106 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2019
A Transient Enhancement DC-DC Buck Converter With Dual Operating Modes Control Technique.
IEEE Trans. on Circuits and Systems, 2019

Frequency Hopping and Parallel Driving With Random Delay Especially Suitable for the Charger Noise Problem in Mutual-Capacitive Touch Applications.
IEEE Access, 2019

Subjective Interpupillary Distance of Measurement Technique.
Proceedings of the 2019 International Symposium on Intelligent Signal Processing and Communication Systems, 2019

2018
A Real Time EEG Analysis System for the Prediction of Clinical Antidepressant Responses.
Proceedings of the 23rd IEEE International Conference on Digital Signal Processing, 2018

2017
An efficient DFT-based algoritiim for the charger noise problem in capacitive touch applications.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016
A 6.7 MHz to 1.24 GHz 0.0318 mm 2 Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS.
J. Solid-State Circuits, 2016

Lossless compression algorithm based on dictionary coding for multiple e-beam direct write system.
Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015
A -194 dBc/Hz FOM interactive current-reused QVCO (ICR-QVCO) with capacitor-coupling self-switching sinusoidal current biasing (CSSCB) phase noise reduction technique.
Proceedings of the Symposium on VLSI Circuits, 2015

A fast-settling high linearity auto gain control for broadband OFDM-based PLC system.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 160MHz-to-2GHz low jitter fast lock all-digital DLL with phase tracking technique.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A 8.1/5.4/2.7/1.62 Gb/s receiver for DisplayPort Version 1.3 with automatic bit-rate tracking scheme.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Bandwidth performance analysis with a variation of Webpage sizes.
Proceedings of the 2015 International Conference on Machine Learning and Cybernetics, 2015

Clustering-based multi-touch algorithm framework for the tracking problem with a large number of points.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014
Current-mode adaptively hysteretic control for buck converters with fast transient response and improved output regulation.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

An efficient multi-touch tracking algorithm with a large number of points.
Proceedings of the IEEE Fourth International Conference on Consumer Electronics Berlin, 2014

Cost-efficient hardware implementation of stereo image depth optimization system.
Proceedings of the 2014 International Conference on 3D Imaging, 2014

2013
A 52 dBc MTPR line driver for powerline communication HomePlug AV standard in 0.18-μm CMOS technology.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A high dynamic range programmable gain amplifier for HomePlug AV powerline communication system.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

A 10-bit current-steering DAC for HomePlug AV2 powerline communication system in 90nm CMOS.
Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012
An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.
IEEE Trans. on Circuits and Systems, 2012

Efficient Thermal Simulation for 3-D IC With Thermal Through-Silicon Vias.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2012

A 6.7MHz-to-1.24GHz 0.0318mm2 fast-locking all-digital DLL in 90nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A 2 - 8 GHz multi-phase distributed DLL using phase insertion in 90 nm.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Equivalent bandwidth model of parallel servers with a variation of CPU loads, system response time and number of users.
Proceedings of the 25th IEEE Canadian Conference on Electrical and Computer Engineering, 2012

2011
A 12 Gb/s chip-to-chip AC coupled transceiver.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A 1.2V 6.4GHz 181ps 64-bit CD domino adder with DLL measurement technique.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

An at-speed self-testable technique for the high speed domino adder.
Proceedings of the 2011 IEEE Custom Integrated Circuits Conference, 2011

Epileptic Seizure Detection for Multichannel EEG Signals with Support Vector Machines.
Proceedings of the 11th IEEE International Conference on Bioinformatics and Bioengineering, 2011

2010
Accurate and Analytical Statistical Spatial Correlation Modeling Based on Singular Value Decomposition for VLSI DFM Applications.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2010

Interconnect delay and slew metrics using the extreme value distribution.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

The compatibility analysis of thread migration and DVFS in multi-core processor.
Proceedings of the 11th International Symposium on Quality of Electronic Design (ISQED 2010), 2010

Interconnect delay and slew metrics using the beta distribution.
Proceedings of the Design, Automation and Test in Europe, 2010

Runtime temperature-based power estimation for optimizing throughput of thermal-constrained multi-core processors.
Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

2008
Wire Sizing.
Proceedings of the Handbook of Algorithms for Physical Design Automation., 2008

Performance measurement and queueing analysis of medium-high blocking probability of two and three parallel connection servers.
Proceedings of the LCN 2008, 2008

Process-Variation Statistical Modeling for VLSI Timing Analysis.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Deep Submicron Interconnect Timing Model with Quadratic Random Variable Analysis.
Proceedings of the Design, Automation and Test in Europe, 2008

Accurate and analytical statistical spatial correlation modeling for VLSI DFM applications.
Proceedings of the 45th Design Automation Conference, 2008

An optimal algorithm for sizing sequential circuits for industrial library based designs.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

LTCC spiral inductor modeling, synthesis, and optimization.
Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007
Numerically Convex Forms and Their Application in Gate Sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2007

3DFFT: Thermal Analysis of Non-Homogeneous IC Using 3D FFT Green Function Method.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design.
Proceedings of the 12th Conference on Asia South Pacific Design Automation, 2007

2006
Correlation-Preserved Statistical Timing With a Quadratic Form of Gaussian Variables.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Statistical static timing analysis with conditional linear MAX/MIN approximation and extended canonical timing model.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2006

Temperature-Aware Placement for SOCs.
Proceedings of the IEEE, 2006

ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems.
Proceedings of the 7th International Symposium on Quality of Electronic Design (ISQED 2006), 2006

Non-gaussian statistical parameter modeling for SSTA with confidence interval analysis.
Proceedings of the 2006 International Symposium on Physical Design, 2006

Simultaneous area minimization and decaps insertion for power delivery network using adjoint sensitivity analysis with IEKS method.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Statistical timing analysis with path reconvergence and spatial correlations.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006

Convergence-provable statistical timing analysis with level-sensitive latches and feedback loops.
Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

2005
HiPRIME: hierarchical and passivity preserved interconnect macromodeling engine for RLKC power delivery.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

EPEEC: comprehensive SPICE-compatible reluctance extraction for high-speed interconnects above lossy multilayer substrates.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2005

Yield-Driven, False-Path-Aware Clock Skew Scheduling.
IEEE Design & Test of Computers, 2005

False Path and Clock Scheduling Based Yield-Aware Gate Sizing.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005

System-level power and thermal modeling and analysis by orthogonal polynomial based response surface approach (OPRS).
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

Efficient statistical capacitance variability modeling with orthogonal principle factor analysis.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005

1-V 7-mW dual-band fast-locked frequency synthesizer.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Statistical Timing Analysis with Extended Pseudo-Canonical Timing Model.
Proceedings of the 2005 Design, 2005

Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model.
Proceedings of the 42nd Design Automation Conference, 2005

ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction.
Proceedings of the 42nd Design Automation Conference, 2005

Block based statistical timing analysis with extended canonical timing model.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Wave-pipelined on-chip global interconnect.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Process-variation robust and low-power zero-skew buffered clock-tree synthesis using projected scan-line sampling.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Comprehensive frequency dependent interconnect extraction and evaluation methodology.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Fast and effective gate-sizing with multiple-Vt assignment using generalized Lagrangian Relaxation.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
Zero skew clock-tree optimization with buffer insertion/sizing and wire sizing.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2004

SPICE-Compatible Thermal Simulation with Lumped Circuit Modeling for Thermal Reliability Analysis Based on Modeling Order Reduction.
Proceedings of the 5th International Symposium on Quality of Electronic Design (ISQED 2004), 2004

Sensitivity guided net weighting for placement driven synthesis.
Proceedings of the 2004 International Symposium on Physical Design, 2004

A yield improvement methodology using pre- and post-silicon statistical clock scheduling.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004

Thermal and Power Integrity Based Power/Ground Networks Optimization.
Proceedings of the 2004 Design, 2004

Realizable Reduction for Electromagnetically Coupled RLMC Interconnects.
Proceedings of the 2004 Design, 2004

SCORE: SPICE COmpatible Reluctance Extraction.
Proceedings of the 2004 Design, 2004

Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining.
Proceedings of the 41th Design Automation Conference, 2004

EPEEC: a compact reluctance based interconnect model considering lossy substrate eddy currents.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

Frequency-dependent reluctance extraction.
Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, 2004

2003
Thermal-ADI - a linear-time chip-level dynamic thermal-simulation algorithm based on alternating-direction-implicit (ADI) method.
IEEE Trans. VLSI Syst., 2003

The power grid transient simulation in linear time based on 3-D alternating-direction-implicit method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

INDUCTWISE: inductance-wise interconnect simulator and extractor.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2003

3D thermal-ADI: an efficient chip-level transient thermal simulator.
Proceedings of the 2003 International Symposium on Physical Design, 2003

Optimal minimum-delay/area zero-skew clock tree wire-sizing in pseudo-polynomial time.
Proceedings of the 2003 International Symposium on Physical Design, 2003

PODEA: Power delivery efficient analysis with realizable model reduction.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

SuPREME: Substrate and Power-delivery Reluctance-Enhanced Macromodel Evaluation.
Proceedings of the 2003 International Conference on Computer-Aided Design, 2003

The Power Grid Transient Simulation in Linear Time Based on 3D Alternating-Direction-Implicit Method .
Proceedings of the 2003 Design, 2003

A hierarchical analysis methodology for chip-level power delivery with realizable model reduction.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

2002
Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on Lagrangian Relaxation.
VLSI Design, 2002

3-D Thermal-ADI: a linear-time chip level transient thermal simulator.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Power grid transient simulation in linear time based on transmission-line-modeling alternating-direction-implicit method.
IEEE Trans. on CAD of Integrated Circuits and Systems, 2002

Optimization of the Power/Ground Network Wire-Sizing and Spacing Based on Sequential Network Simplex Algorithm.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

Future SoC Design Challenges and Solutions (invited).
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002

INDUCTWISE: inductance-wise interconnect simulator and extractor.
Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, 2002

HiPRIME: hierarchical and passivity reserved interconnect macromodeling engine for RLKC power delivery.
Proceedings of the 39th Design Automation Conference, 2002

2001
RC-in RC-out Model Order Reduction Accurate up to Second Order Moments.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Linear Time Hierarchical Capacitance Extraction without Multipole Expansion.
Proceedings of the 19th International Conference on Computer Design (ICCD 2001), 2001

Hierarchical model order reduction for signal-integrity interconnect synthesis.
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001

Efficient Large-Scale Power Grid Analysis Based on Preconditioned Krylov-Subspace Iterative Methods.
Proceedings of the 38th Design Automation Conference, 2001

Optimal spacing and capacitance padding for general clock structures.
Proceedings of ASP-DAC 2001, 2001

2000
Generalized FDTD-ADI: An Unconditionally Stable Full-Wave Maxwell's Equations Solver for VLSI Interconnect Modeling.
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

1999
Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation.
IEEE Trans. on CAD of Integrated Circuits and Systems, 1999

Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999

Error Bounded Padé Approximation via Bilinear Conformal Transformation.
Proceedings of the 36th Conference on Design Automation, 1999

Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching.
Proceedings of the 36th Conference on Design Automation, 1999

1997
Optimal Wire-Sizing Function with Fringing Capacitance Consideration.
Proceedings of the 34st Conference on Design Automation, 1997

1996
Optimal non-uniform wire-sizing under the Elmore delay model.
Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, 1996

Optimal Wire-Sizing Formular Under the Elmore Delay Model.
Proceedings of the 33st Conference on Design Automation, 1996

Fast Performance-Driven Optimization for Buffered Clock Trees Based on Lagrangian Relaxation.
Proceedings of the 33st Conference on Design Automation, 1996


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