Huanlin Xie

According to our database, Huanlin Xie authored at least 5 papers in 2025.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2025

A 9-GHz Low-In-Band Noise Sub-Sampling-Chopper PLL With Charge-Share Canceling Technique.

Xiangjian Kong, Kai Xu, Huanlin Xie, Mingchao Jian, Hao Lian, Robert Bogdan Staszewski, Chunbing Guo

IEEE J. Solid State Circuits, April, 2025

A 24-kHz bandwidth 94.8-dB-SNDR discrete-time dynamic zoom ADC with analog-domain combine.

Zhenyu Wang, Huanlin Xie, Mingchao Jian, Mingtao Hu, Bo Sun, Chunbing Guo

Microelectron. J., 2025

A time-interleaved 2b/Cycle SAR ADC with sign-inversion method for timing-skew calibration.

Jiawei Tian, Mingchao Jian, Huanlin Xie, Mingjie Li, Jiajun Yang, Chunbing Guo

Microelectron. J., 2025

A 2-MHz BW 93.2-dB SFDR 2nd-Order Hybrid EF-CIFF Noise Shaping SAR ADC.

Mingjie Li, Mingchao Jian, Huanlin Xie, Jiajun Yang, Jiawei Tian, Bo Sun, Chunbing Guo

Microelectron. J., 2025

An 80-MS/s 60.9-dB SNDR Fully Differential Ring Amplifier-Based SAR-Assisted Pipelined ADC With Dual Redundancy in 65-nm CMOS.

Hao Chen, Mingchao Jian, Zhenyu Wang, Huanlin Xie, Bo Sun, Chunbing Guo

Int. J. Circuit Theory Appl., 2025