Robert Bogdan Staszewski
Orcid: 0000-0001-9848-1129Affiliations:
- University College Dublin, School of Electrical and Electronic Engineering, Ireland
- University of Texas at Dallas, TX, USA (PhD 2002)
According to our database1,
Robert Bogdan Staszewski
authored at least 245 papers
between 1997 and 2024.
Collaborative distances:
Collaborative distances:
Awards
IEEE Fellow
IEEE Fellow 2009, "For contributions to development of digital radio frequency integrated systems".
Timeline
Legend:
Book In proceedings Article PhD thesis Dataset OtherLinks
Online presence:
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on bogdanst.com
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on orcid.org
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on id.loc.gov
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on d-nb.info
On csauthors.net:
Bibliography
2024
A Fully Integrated QPSK/16-QAM D-Band CMOS Transceiver With Mixed-Signal Baseband Circuitry Realizing Digital Interfaces.
IEEE J. Solid State Circuits, October, 2024
IEEE Trans. Circuits Syst. II Express Briefs, March, 2024
A 25.4-27.5 GHz Ping-Pong Charge-Sharing Locking PLL Achieving 42 fs Jitter with Implicit Reference Frequency Doubling.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 9-GHz Subsampling-Chopper PLL with Charge-Share Cancelling and Achieving 57.8-fs-rms Jitter with 15dB In-Band Noise Improvement.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion.
IEEE J. Solid State Circuits, September, 2023
An On-Chip Picoampere-Level Leakage Current Sensor for Quantum Processors in 22-nm FD-SOI CMOS.
IEEE Trans. Circuits Syst. II Express Briefs, June, 2023
A Compact, Low-Power, Low-NF, Millimeter-Wave Cascode LNA With Magnetic Coupling Feedback in 22-nm FD-SOI CMOS for 5G Applications.
IEEE Trans. Circuits Syst. II Express Briefs, April, 2023
Exploring Speed Maximization of Frequency-to-Digital Conversion for Ultra-Low-Voltage VCO-Based ADCs.
IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023
IEEE Trans. Circuits Syst. II Express Briefs, February, 2023
IEEE J. Solid State Circuits, 2023
A 30-GHz Class-F Quadrature DCO Using Phase Shifts Between Drain-Gate-Source for Low Flicker Phase Noise and I/Q Exactness.
IEEE J. Solid State Circuits, 2023
A 50μW Ring-Type Complementary Inverse-Class-D Oscillator with 191.4dBc/Hz FoM and 205.6dBc/Hz FoMA.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
An 18.8-to-23.3 GHz ADPLL Based on Charge-Steering-Sampling Technique Achieving 75.9 fs RMS Jitter and -252 dB FoM.
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Scalable multi-chip quantum architectures enabled by cryogenic hybrid wireless/quantum-coherent network-in-package.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
IEEE Trans. Circuits Syst. II Express Briefs, 2022
A Broadband Fully Integrated Power Amplifier Using Waveform Shaping Multi-Resonance Harmonic Matching Network.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A G<sub>m</sub>-Boosting Technique for Millimeter-Wave Low-Noise Amplifiers in 28-nm Triple-Well Bulk CMOS Using Floating Resistor in Body Biasing.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 529-μW Fractional-N All-Digital PLL Using TDC Gain Auto-Calibration and an Inverse-Class-F DCO in 65-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
Flicker Phase-Noise Reduction Using Gate-Drain Phase Shift in Transformer-Based Oscillators.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
A 20 MHz-2 GHz Inductorless Two-Fold Noise-Canceling Low-Noise Amplifier in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2022
IEEE J. Solid State Circuits, 2022
A Charge-Sharing Locking Technique With a General Phase Noise Theory of Injection Locking.
IEEE J. Solid State Circuits, 2022
A Compact 0.2-0.3-V Inverse-Class-F<sub>23</sub> Oscillator for Low 1/f<sup>3</sup> Noise Over Wide Tuning Range.
IEEE J. Solid State Circuits, 2022
A Fractional-N Digitally Intensive PLL Achieving 428-fs Jitter and <sub>pp</sub> Supply Ripple.
IEEE J. Solid State Circuits, 2022
IEEE J. Solid State Circuits, 2022
IEEE J. Solid State Circuits, 2022
A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022
A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022
Control of Quantum Systems: Comparison of Different Techniques by the Example of Charge and Spin Semiconductor Qubits.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Cryogenic Transistor Confinement Well Simulation through Material and Carrier Transport Decoupling.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Modelling of Electron Injection and Confinement in Cryogenic 22-nm FD-SOI Quantum Dot Arrays.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
Characterisation and Modelling of 22-nm FD-SOI Transistors Operating at Cryogenic Temperatures.
Proceedings of the 29th IEEE International Conference on Electronics, Circuits and Systems, 2022
2021
A Fully Integrated GaN Dual-Channel Power Amplifier With Crosstalk Suppression for 5G Massive MIMO Transmitters.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. II Express Briefs, 2021
A 38.6-fJ/Conv.-Step Inverter-Based Continuous-Time Bandpass ΔΣ ADC in 28 nm Using Asynchronous SAR Quantizer.
IEEE Trans. Circuits Syst. II Express Briefs, 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
IEEE Trans. Circuits Syst. I Regul. Pap., 2021
Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS.
IEEE Open J. Circuits Syst., 2021
Towards the Co-Simulation of Charge Qubits: A Methodology Grounding on an Equivalent Circuit Representation.
IEEE Open J. Circuits Syst., 2021
IEEE Open J. Circuits Syst., 2021
A Distributed Stubs Technique to Mitigate Flicker Noise Upconversion in a mm-Wave Rotary Traveling-Wave Oscillator.
IEEE J. Solid State Circuits, 2021
Unbalanced Power Amplifier: An Architecture for Broadband Back-Off Efficiency Enhancement.
IEEE J. Solid State Circuits, 2021
IEEE J. Solid State Circuits, 2021
A 0.02-4.5-GHz LN(T)A in 28-nm CMOS for 5G Exploiting Noise Reduction and Current Reuse.
IEEE J. Solid State Circuits, 2021
Monolithic Integration of Quantum Resonant Tunneling Gate on a 22nm FD-SOI CMOS Process.
CoRR, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
A Feedforward and Feedback Constant-Slope Digital-to-Time Converter in 28nm CMOS Achieving ≤ 0.12% INL/Range over >100mV Supply Range.
Proceedings of the 2021 Symposium on VLSI Circuits, Kyoto, Japan, June 13-19, 2021, 2021
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
Proceedings of the 51st IEEE European Solid-State Device Research Conference, 2021
A 28-GHz Switched-Filter Phase Shifter with Fine Phase-Tuning Capability Using Back-Gate Biasing in 22-nm FD-SOI CMOS.
Proceedings of the 47th ESSCIRC 2021, 2021
Proceedings of the 47th ESSCIRC 2021, 2021
2020
A Time-Domain 147fs<sub>rms 2.5</sub>-MHz Bandwidth Two-Step Flash-MASH 1-1-1 Time-to-Digital Converter With Third-Order Noise-Shaping and Mismatch Correction.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
An Adaptive-Resolution Quasi-Level-Crossing Delta Modulator With VCO-Based Residue Quantizer.
IEEE Trans. Circuits Syst., 2020
A Switched-Capacitor DC-DC Converter Powering an LC Oscillator to Achieve 85% System Peak Power Efficiency and -65dBc Spurious Tones.
IEEE Trans. Circuits Syst., 2020
Design Considerations of the Interpolative Digital Transmitter for Quantization Noise and Replicas Rejection.
IEEE Trans. Circuits Syst. II Express Briefs, 2020
Broadband Fully Integrated GaN Power Amplifier With Minimum-Inductance BPF Matching and Two-Transistor AM-PM Compensation.
IEEE Trans. Circuits Syst., 2020
IEEE Trans. Circuits Syst., 2020
A 0.36-V 5-MS/s Time-Mode Flash ADC With Dickson-Charge-Pump-Based Comparators in 28-nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Mismatch Calibration Technique for SAR ADCs Based on Deterministic Self-Calibration and Stochastic Quantization.
IEEE Trans. Circuits Syst. I Regul. Pap., 2020
A Single-Pin Antenna Interface RF Front End Using a Single-MOS DCO-PA and a Push-Pull LNA.
IEEE J. Solid State Circuits, 2020
IEEE J. Solid State Circuits, 2020
IEEE Access, 2020
30.8 A 3.5mm×3.8mm Crystal-Less MICS Transceiver Featuring Coverages of ±160ppm Carrier Frequency Offset and 4.8-VSWR Antenna Impedance for Insertable Smart Pills.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
17.6 A 21.7-to-26.5GHz Charge-Sharing Locking Quadrature PLL with Implicit Digital Frequency-Tracking Loop Achieving 75fs Jitter and -250dB FoM.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Proceedings of the Computational Science - ICCS 2020, 2020
2019
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2019
A Low-Noise Fractional- ${N}$ Digital Frequency Synthesizer With Implicit Frequency Tripling for mm-Wave Applications.
IEEE J. Solid State Circuits, 2019
A 0.85mm<sup>2</sup> 51%-Efficient 11-dBm Compact DCO-DPA in 16-nm FinFET for Sub-Gigahertz IoT TX Using HD<sub>2</sub> Self-Suppression and Pulling Mitigation.
IEEE J. Solid State Circuits, 2019
IEEE J. Solid State Circuits, 2019
A 1-V Bandgap Reference in 7-nm FinFET With a Programmable Temperature Coefficient and Inaccuracy of ±0.2% From -45°C to 125°C.
IEEE J. Solid State Circuits, 2019
A 31-µW, 148-fs Step, 9-bit Capacitor-DAC-Based Constant-Slope Digital-to-Time Converter in 28-nm CMOS.
IEEE J. Solid State Circuits, 2019
A Supply Pushing Reduction Technique for LC Oscillators Based on Ripple Replication and Cancellation.
IEEE J. Solid State Circuits, 2019
Bandwidth Enhancement of GaN MMIC Doherty Power Amplifiers Using Broadband Transformer-Based Load Modulation Network.
IEEE Access, 2019
IEEE Access, 2019
Challenges in On-Chip Antenna Design and Integration With RF Receiver Front-End Circuitry in Nanoscale CMOS for 5G Communication Systems.
IEEE Access, 2019
Modeling of Semiconductor Electrostatic Qubits Realized Through Coupled Quantum Dots.
IEEE Access, 2019
28 GHz Quadrature Frequency Generation Exploiting Injection-Locked Harmonic Extractors for 5G Communications.
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
Proceedings of the 17th IEEE International New Circuits and Systems Conference, 2019
A Python-Verilog Toolbox for Modeling of a Hadamard Gate Based on Position-Based CMOS Qubits.
Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019
A 184.6-dBc/Hz FoM 100-kHz Flicker Phase Noise Corner 30-GHz Rotary Traveling-Wave Oscillator Using Distributed Stubs in 22-nm FD-SOI.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Broadband Fully Integrated GaN Power Amplifier With Embedded Minimum Inductor Bandpass Filter and AM-PM Compensation.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A 77/79-GHz Frequency Generator in 16-nm CMOS for FMCW Radar Applications Based on a 26-GHz Oscillator with Co-Generated Third Harmonic.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
A Mixed-Signal Control Core for a Fully Integrated Semiconductor Quantum Computer System-on-Chip.
Proceedings of the 45th IEEE European Solid State Circuits Conference, 2019
Behavioral Modelling and Optimization of a Cyclic Feedback-Based Successive Approximation TDC with Dynamic Delay Equalization.
Proceedings of the 5th International Conference on Event-Based Control, 2019
A 0.3V, 35% Tuning-Range, 60kHz 1/f<sup>3</sup>-Corner Digitally Controlled Oscillator with Vertically Integrated Switched Capacitor Banks Achieving FoMT of -199dB in 28-nm CMOS.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2019
DTC-Assisted All-Digital Phase-Locked Loop Exploiting Hybrid Time/Voltage Phase Digitization.
Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019
2018
An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
An On-Chip Self-Characterization of a Digital-to-Time Converter by Embedding it in a First-Order ΔΣ Loop.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS.
IEEE J. Solid State Circuits, 2018
IEEE J. Solid State Circuits, 2018
All-Digital PLL for Bluetooth Low Energy Using 32.768-kHz Reference Clock and ≤0.45-V Supply.
IEEE J. Solid State Circuits, 2018
A Low-Flicker-Noise 30-GHz Class-F<sub>23</sub> Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path.
IEEE J. Solid State Circuits, 2018
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW.
Proceedings of the 2018 IEEE Symposium on VLSI Circuits, 2018
A 0.45V sub-mW all-digital PLL in 16nm FinFET for bluetooth low-energy (BLE) modulation and instantaneous channel hopping using 32.768kHz reference.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018
Occupancy Oscillations and Electron Transfer in Multiple-Quantum-Dot Qubits and their Circuit Representation.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018
BJT Device and Circuit Co-Optimization Enabling Bandgap Reference and Temperature Sensing in 7-nm FinFET.
Proceedings of the 48th European Solid-State Device Research Conference, 2018
A 1 V Bandgap Reference in 7-nm FinFET with a Programmable Temperature Coefficient and an Inaccuracy of ±0.2% from -45°C to 125°C.
Proceedings of the 44th IEEE European Solid State Circuits Conference, 2018
A 2.4-GHz Single-Pin Antenna Interface RF Front-End with a Function-Reuse Single-MOS VCO-PA and a Push-Pull LNA.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Tuning Range Extension of a Transformer-Based Oscillator Through Common-Mode Colpitts Resonance.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
An Ultra-Low Power 1.7-2.7 GHz Fractional-N Sub-Sampling Digital Frequency Synthesizer and Modulator for IoT Applications in 40 nm CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2017
A 3.5-6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH ΔΣ-TDC for Low In-Band Phase Noise.
IEEE J. Solid State Circuits, 2017
A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network.
IEEE J. Solid State Circuits, 2017
Introduction to the Special Issue on the 46th European Solid-State Circuits Conference (ESSCIRC).
IEEE J. Solid State Circuits, 2017
24.1 A 770pJ/b 0.85V 0.3mm<sup>2</sup> DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applications.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017
A 30-GHz class-F23 oscillator in 28nm CMOS using harmonic extraction and achieving 120 kHz 1/f<sup>3</sup> corner.
Proceedings of the 43rd IEEE European Solid State Circuits Conference, 2017
Proceedings of the 3rd International Conference on Event-Based Control, 2017
Proceedings of the 3rd International Conference on Event-Based Control, 2017
A 15-μW, 103-fs step, 5-bit capacitor-DAC-based constant-slope digital-to-time converter in 28nm CMOS.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
A 350-mV 2.4-GHz quadrature oscillator with nearly instantaneous start-up using series LC tanks.
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2017
2016
Toward Solving Multichannel RF-SoC Integration Issues Through Digital Fractional Division.
IEEE Trans. Very Large Scale Integr. Syst., 2016
IEEE Trans. Circuits Syst. I Regul. Pap., 2016
A 60 GHz Frequency Generator Based on a 20 GHz Oscillator and an Implicit Multiplier.
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
IEEE J. Solid State Circuits, 2016
A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm.
IEEE J. Solid State Circuits, 2016
A Wideband Digital-to-Frequency Converter with Built-In Mechanism for Self-Interference Mitigation.
J. Electron. Test., 2016
A 0.034mm<sup>2</sup>, 725fs RMS jitter, 1.8%/V frequency-pushing, 10.8-19.3GHz transformer-based fractional-N all-digital PLL in 10nm FinFET CMOS.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise.
Proceedings of the ESSCIRC Conference 2016: 42<sup>nd</sup> European Solid-State Circuits Conference, 2016
Proceedings of the Second International Conference on Event-based Control, 2016
A 0.5ps 1.4mW 50MS/s Nyquist bandwidth time amplifier based two-step flash-ΔΣ time-to-digital converter.
Proceedings of the Second International Conference on Event-based Control, 2016
2015
Design of Spur-Free ΣΔ Frequency Tuning Interface for Digitally Controlled Oscillators.
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Analysis and Design of I/Q Charge-Sharing Band-Pass-Filter for Superheterodyne Receivers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2015
An Ultra-Low Phase Noise Class-F 2 CMOS Oscillator With 191 dBc/Hz FoM and Long-Term Reliability.
IEEE J. Solid State Circuits, 2015
A TDD/FDD SAW-less superheterodyne receiver with blocker-resilient band-pass filter and multi-stage HR in 28nm CMOS.
Proceedings of the Symposium on VLSI Circuits, 2015
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
25.4 A 1/f noise upconversion reduction technique applied to Class-D and Class-F oscillators.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015
A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015
A fully integrated 28nm Bluetooth Low-Energy transmitter with 36% system efficiency at 3dBm.
Proceedings of the ESSCIRC Conference 2015, 2015
Design and built-in characterization of digital-to-time converters for ultra-low power ADPLLs.
Proceedings of the ESSCIRC Conference 2015, 2015
2014
A 56.4-to-63.4 GHz Multi-Rate All-Digital Fractional-N PLL for FMCW Radar Applications in 65 nm CMOS.
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
IEEE J. Solid State Circuits, 2014
IPSJ Trans. Syst. LSI Des. Methodol., 2014
Proceedings of the Symposium on VLSI Circuits, 2014
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
9.8 An 860μW 2.1-to-2.7GHz all-digital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 2014
2013
High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators.
IEEE J. Solid State Circuits, 2013
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 2mW 800MS/s 7th-order discrete-time IIR filter with 400kHz-to-30MHz BW and 100dB stop-band rejection in 65nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
A 0.27mm<sup>2</sup> 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Third-harmonic injection technique applied to a 5.87-to-7.56GHz 65nm CMOS Class-F oscillator with 192dBc/Hz FOM.
Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013
Frequency translation through fractional division for a two-channel pulling mitigation.
Proceedings of the ESSCIRC 2013, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
Proceedings of the 21st European Conference on Circuit Theory and Design, 2013
2012
A clip-and-restore technique for phase desensitization in a 1.2V 65nm CMOS oscillator for cellular mobile and base stations.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012
2011
Spurious-Free Time-to-Digital Conversion in an ADPLL Using Short Dithering Sequences.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
State-of-the-Art and Future Directions of High-Performance All-Digital Frequency Synthesis in Nanometer CMOS.
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE Trans. Circuits Syst. I Regul. Pap., 2011
IEEE J. Solid State Circuits, 2011
IEEE J. Solid State Circuits, 2011
IEICE Trans. Electron., 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the IEEE International Solid-State Circuits Conference, 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the 20th European Conference on Circuit Theory and Design, 2011
Proceedings of the IEEE Asian Solid-State Circuits Conference, 2011
2010
A Technique to Reduce Phase/Frequency Modulation Bandwidth in a Polar RF Transmitter.
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. I Regul. Pap., 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
IEEE Trans. Circuits Syst. II Express Briefs, 2010
Software Assisted Digital RF Processor (DRP™) for Single-Chip GSM Radio in 90 nm CMOS.
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
Spurious free time-to-digital conversion in an ADPLL using short dithering sequences.
Proceedings of the IEEE Custom Integrated Circuits Conference, 2010
2009
A Phase Domain Approach for Mitigation of Self-Interference in Wireless Transceivers.
IEEE J. Solid State Circuits, 2009
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009
2008
IEEE Trans. Circuits Syst. II Express Briefs, 2008
A 24mm<sup>2</sup> Quad-Band Single-Chip GSM Radio with Transmitter Calibration in 90nm Digital CMOS.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008
Curse of digital polar transmission: Precise delay alignment in amplitude and phase modulation paths.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Mitigation of CMOS device variability in the transmitter amplitude path using Digital RF Processing.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE Trans. Circuits Syst. II Express Briefs, 2007
IEEE J. Solid State Circuits, 2007
On the Reconfigurability of All-Digital Phase-Locked Loops for Software Defined Radios.
Proceedings of the IEEE 18th International Symposium on Personal, 2007
Proceedings of the 2007 IEEE International Solid-State Circuits Conference, 2007
Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its Mitigation.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOS.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Time-Domain Modeling of a Phase-Domain All-Digital Phase-Locked Loop for RF Applications.
Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007
2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
IEEE Trans. Circuits Syst. II Express Briefs, 2006
The First Fully Integrated Quad-Band GSM/GPRS Receiver in a 90-nm Digital CMOS Process.
IEEE J. Solid State Circuits, 2006
A digitally controlled oscillator system for SAW-less transmitters in cellular handsets.
IEEE J. Solid State Circuits, 2006
A Sigma-Delta ADC with Decimation and Gain Control Function for a Bluetooth Receiver in 130 nm Digital CMOS.
EURASIP J. Wirel. Commun. Netw., 2006
Charge-Domain Signal Processing of Direct RF Sampling Mixer with Discrete-Time Filters in Bluetooth and GSM Receivers.
EURASIP J. Wirel. Commun. Netw., 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
Proceedings of the IEEE 2006 Custom Integrated Circuits Conference, 2006
2005
IEEE Trans. Very Large Scale Integr. Syst., 2005
Direct frequency modulation of an ADPLL for bluetooth/GSM with injection pulling elimination.
IEEE Trans. Circuits Syst. II Express Briefs, 2005
IEEE Trans. Circuits Syst. I Regul. Pap., 2005
IEEE Trans. Circuits Syst. II Express Briefs, 2005
IEEE J. Solid State Circuits, 2005
IEEE J. Solid State Circuits, 2005
IEEE Commun. Mag., 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Sigma-Delta Noise Shaping for Digital-to-Frequency and Digital-to-RF-Amplitude Conversion.
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 5th IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC 2005), 2005
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Characterization of deep-submicron varactor mismatches in a digitally controlled oscillator.
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
Proceedings of the IEEE 2005 Custom Integrated Circuits Conference, 2005
2004
All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS.
IEEE J. Solid State Circuits, 2004
Event-driven simulation and modeling of an RF oscillator.
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
Proceedings of the 2004 International Symposium on Circuits and Systems, 2004
A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004
2003
Digitally controlled oscillator (DCO)-based architecture for RF frequency synthesis in a deep-submicrometer CMOS Process.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Just-in-time gain estimation of an RF digitally-controlled oscillator for digital direct frequency modulation.
IEEE Trans. Circuits Syst. II Express Briefs, 2003
Proceedings of the IEEE Custom Integrated Circuits Conference, 2003
2001
Speed, power, area, and latency tradeoffs in adaptive FIR filtering for PRML read channels.
IEEE Trans. Very Large Scale Integr. Syst., 2001
Proceedings of the 11th ACM Great Lakes Symposium on VLSI 2001, 2001
2000
IEEE J. Solid State Circuits, 2000
Low power techniques and design tradeoffs in adaptive FIR filtering for PRML read channels.
Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000
1997
IEEE J. Solid State Circuits, 1997