Huyen Thi Pham

Orcid: 0000-0001-7222-5071

According to our database1, Huyen Thi Pham authored at least 5 papers between 2015 and 2018.

Collaborative distances:
  • Dijkstra number2 of six.
  • Erdős number3 of five.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2018
Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields.
IEEE Trans. Very Large Scale Integr. Syst., 2018

2017
Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes.
IEEE Trans. Very Large Scale Integr. Syst., 2017

High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes.
Integr., 2017

2016
Low latency check node unit architecture for nonbinary LDPC decoding.
Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015
Parallel block-layered nonbinary QC-LDPC decoding on GPU.
Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015


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