Hanho Lee

IEEE Trans. Circuits Syst. I Regul. Pap., December, 2023

Configurable Memory-Based NTT Architecture for Homomorphic Encryption.

[BibT_eX]

[DOI]

Stefanus Kurniawan

IEEE Trans. Circuits Syst. II Express Briefs, October, 2023

Configurable Encryption and Decryption Architectures for CKKS-Based Homomorphic Encryption.

[BibT_eX]

[DOI]

Jaehyeok Lee

Sensors, September, 2023

Hamming-Distance Trellis Min-Max-Based Architecture for Non-Binary LDPC Decoder.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, July, 2023

Area-Efficient Number Theoretic Transform Architecture for Homomorphic Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., March, 2023

Pipelined Key Switching Accelerator Architecture for CKKS-Based Fully Homomorphic Encryption.

[BibT_eX]

[DOI]

Sensors, 2023

Twiddle Factor Generator Architecture for Number Theoretic Transform.

[BibT_eX]

[DOI]

Proceedings of the 20th International SoC Design Conference, 2023

CKKS-Based Homomorphic Encryption Architecture using Parallel NTT Multiplier.

[BibT_eX]

[DOI]

Jisu Kim

Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2022

Efficient First Four Minimum Values Finder for NB-LDPC Decoders With Compressed Messages.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2022

Low-Complexity Multi-Size Circular-Shift Network for 5G New Radio LDPC Decoders.

[BibT_eX]

[DOI]

Tram Thi Bao Nguyen

Sensors, 2022

Configurable Mixed-Radix Number Theoretic Transform Architecture for Lattice-Based Cryptography.

[BibT_eX]

[DOI]

IEEE Access, 2022

Low-Complexity Architecture of Finding First Four Minimum Values for Non-binary LDPC Decoders.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

Flexible GPU-Based Implementation of Number Theoretic Transform for Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 19th International SoC Design Conference, 2022

Toward A Real-Time Elliptic Curve Cryptography-Based Facial Security System.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuit and Systems, 2022

2021

Minimal-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Novel Performance Evaluation Approach of AMBA AXI-Based SoC Design.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

Configurable Butterfly Unit Architecture for NTT/INTT in Homomorphic Encryption.

[BibT_eX]

[DOI]

Proceedings of the 18th International SoC Design Conference, 2021

High-Efficient Nonbinary LDPC Decoder with Early Layer Decoding Schedule.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2021

2020

Efficient NewHope Cryptography Based Facial Security System on a GPU.

[BibT_eX]

[DOI]

IEEE Access, 2020

Efficient Check Node Unit Architecture for Non-binary Quasi-Cyclic LDPC Codes.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2020

Efficient $k$-Parallel Pipelined NTT Architecture for Post Quantum Cryptography.

[BibT_eX]

[DOI]

Yong-Jin Kim

Proceedings of the International SoC Design Conference, 2020

2019

Half-row modified two-extra-column trellis min-max decoder architecture for nonbinary LDPC codes.

[BibT_eX]

[DOI]

Huyen Pham Thi

Xuan Nghia Pham

Integr., 2019

Low-complexity multi-mode multi-way split-row layered LDPC decoder for gigabit wireless communications.

[BibT_eX]

[DOI]

Tram Thi Bao Nguyen

Integr., 2019

High-Secure Fingerprint Authentication System Using Ring-LWE Cryptography.

[BibT_eX]

[DOI]

IEEE Access, 2019

Simplified Variable Node Unit Architecture for Nonbinary LDPC Decoder.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Asia Pacific Conference on Circuits and Systems, 2019

2018

Basic-Set Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes With High-Order Galois Fields.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2018

Efficient Four-way Row-splitting Layered QC-LDPC Decoder Architecture.

[BibT_eX]

[DOI]

Tram Thi Bao Nguyen

Proceedings of the International SoC Design Conference, 2018

High-Secure Low-Latency Ring-LWE Cryptography Scheme for Biomedical Images Storing and Transmitting.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Reduced-Complexity Trellis Min-Max Decoder for Non-Binary Ldpc Codes.

[BibT_eX]

[DOI]

Huyen Pham Thi

Proceedings of the 2018 IEEE International Conference on Acoustics, 2018

2017

Two-Extra-Column Trellis Min-Max Decoder Architecture for Nonbinary LDPC Codes.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2017

High-throughput partial-parallel block-layered decoding architecture for nonbinary LDPC codes.

[BibT_eX]

[DOI]

Integr., 2017

Parallel architecture for concatenated polar-CRC codes.

[BibT_eX]

[DOI]

Seunghun Oh

Proceedings of the International SoC Design Conference, 2017

A delay-efficient ring-LWE cryptography architecture for biometric security.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

2016

Low latency check node unit architecture for nonbinary LDPC decoding.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE Asia Pacific Conference on Circuits and Systems, 2016

2015

Block-Layered Decoder Architecture for Quasi-Cyclic Nonbinary LDPC Codes.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2015

Efficient multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad applications.

[BibT_eX]

[DOI]

Integr., 2015

Parallel block-layered nonbinary QC-LDPC decoding on GPU.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Workshop on Signal Processing Systems, 2015

2014

An efficient radix-4 Quasi-cyclic shift network for QC-LDPC decoders.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Multi-Gb/s multi-mode LDPC decoder architecture for IEEE 802.11ad standard.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013

Block-Circulant RS-LDPC Code: Code Construction and Efficient Decoder Design.

[BibT_eX]

[DOI]

Seong-In Hwang

IEEE Trans. Very Large Scale Integr. Syst., 2013

A High-Speed Low-Complexity Modified Radix-25 FFT Processor for High Rate WPAN Applications.

[BibT_eX]

[DOI]

Taesang Cho

IEEE Trans. Very Large Scale Integr. Syst., 2013

High-performance iterative BCH decoder architecture for 100 Gb/s optical communications.

[BibT_eX]

[DOI]

Jewong Yeon

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

2012

A High-Speed Low-Complexity Concatenated BCH Decoder Architecture for 100 Gb/s Optical Communications.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Implementations of Signal-Processing Algorithms for OFDM Systems.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2012

A High-Speed Low-Complexity Time-Multiplexing Reed-Solomon-Based FEC Architecture for Optical Communications.

[BibT_eX]

[DOI]

Jeong-In Park

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2012

An ultra high-speed time-multiplexing Reed-Solomon-based FEC architecture.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2012

A novel method of constructing Quasi-Cyclic RS-LDPC codes for 10GBASE-T Ethernet.

[BibT_eX]

[DOI]

Seong-In Hwang

Shin-Il Lim

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Concatenated non-binary LDPC and HD-FEC codes for 100Gb/s optical transport systems.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Biochemical sensor interface circuits with differential difference amplifier.

[BibT_eX]

[DOI]

Shin-Il Lim

In-Sub Choi

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2012

2011

A Reduced-Complexity Architecture for LDPC Layered Decoding Schemes.

[BibT_eX]

[DOI]

Sangmin Kim

IEEE Trans. Very Large Scale Integr. Syst., 2011

Low Complexity Filter Architecture for ATSC Terrestrial Broadcasting DTV Systems.

[BibT_eX]

[DOI]

Yong-Kyu Kim

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

Low-Complexity Multi-Mode Memory-Based FFT Processor for DVB-T2 Applications.

[BibT_eX]

[DOI]

Kisun Jung

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2011

High-Throughput Low-Complexity Four-Parallel Reed-Solomon Decoder Architecture for High-Rate WPAN Systems.

[BibT_eX]

[DOI]

Hyo-Jin Ahn

IEICE Trans. Commun., 2011

Low-complexity filter and interpolator design for ATSC DTV systems.

[BibT_eX]

[DOI]

Proceedings of the International SoC Design Conference, 2011

An area-efficient truncated inversionless Berlekamp-Massey architecture for Reed-Solomon decoders.

[BibT_eX]

[DOI]

Jeong-In Park

Seongsoo Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A high-speed low-complexity modified radix-25 FFT processor for gigabit WPAN applications.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

A high-throughput LDPC decoder architecture for high-rate WPAN systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

2010

High-Speed Two-Parallel Concatenated BCH-Based Super-FEC Architecture for Optical Communications.

[BibT_eX]

[DOI]

Sangho Yoon

Kihoon Lee

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2010

Low-cost variable-length FFT processor for DVB-T/H applications.

[BibT_eX]

[DOI]

Kisun Jung

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009

Two-parallel concatenated BCH super-FEC architecture for 100-GB/S optical communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2009

High-speed low-complexity three-parallel reed-solomon decoder for 6-Gbps mmWave WPAN systems.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

2008

A High-Speed Two-Parallel Radix-24 FFT/IFFT Processor for MB-OFDM UWB Systems.

[BibT_eX]

[DOI]

Jeesung Lee

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders.

[BibT_eX]

[DOI]

Seungbeom Lee

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2008

Two-parallel Reed-Solomon based FEC architecture for optical communications.

[BibT_eX]

[DOI]

Seungbeom Lee

IEICE Electron. Express, 2008

A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders.

[BibT_eX]

[DOI]

Sangho Yoon

Proceedings of the 21st Annual IEEE International SoC Conference, SoCC 2008, 2008

A high-speed four-parallel radix-24 FFT/IFFT processor for UWB applications.

[BibT_eX]

[DOI]

Minhyeok Shin

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Adaptive quantization in min-sum based irregular LDPC decoder.

[BibT_eX]

[DOI]

Sangmin Kim

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Two bit-level pipelined viterbi decoder for high-performance UWB applications.

[BibT_eX]

[DOI]

Yong-Je Goo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

A high performance four-parallel 128/64-point radix-24 FFT/IFFT processor for MIMO-OFDM systems.

[BibT_eX]

[DOI]

Hang Liu

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

40-Gb/s two-parallel Reed-Solomon based Forward Error Correction architecture for optical communications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

Flexible LDPC decoder architecture for high-throughput applications.

[BibT_eX]

[DOI]

Sangmin Kim

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2008

2007

A Design and Performance of 4-Parallel MB-OFDM UWB Receiver.

[BibT_eX]

[DOI]

IEICE Trans. Commun., 2007

A Self-Reconfigurable Adaptive FIR Filter System on Partial Reconfiguration Platform.

[BibT_eX]

[DOI]

IEICE Trans. Inf. Syst., 2007

A Partial Self-Reconfigurable Adaptive FIR Filter System.

[BibT_eX]

[DOI]

Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon Decoders.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Ubiquitous Evolvable Hardware System for Heart Disease Diagnosis Applications.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2007

2006

Implementation of a FIR Filter on a Partial Reconfigurable Platform.

[BibT_eX]

[DOI]

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2006

A reconfigurable FIR filter design using dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Yeong-Jae Oh

Chong Ho Lee

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

A high-speed, low-complexity radix-24 FFT processor for MB-OFDM UWB systems.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Dynamic Partial Reconfigurable FIR Filter Design.

[BibT_eX]

[DOI]

Yeong-Jae Oh

Chong Ho Lee

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005

A high-speed low-complexity Reed-Solomon decoder for optical communications.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2005

Power-Aware Scalable Pipelined Booth Multiplier.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2005

Reconfigurable Power-Aware Scalable Booth Multiplier.

[BibT_eX]

[DOI]

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005

An Evolvable Hardware System Under Uneven Environment.

[BibT_eX]

[DOI]

In Ja Jeon

Phill-Kyu Rhee

Proceedings of the Knowledge-Based Intelligent Information and Engineering Systems, 2005

An ultra high-speed Reed-Solomon decoder.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

2004

VLSI Design Of Digit-Serial FPGA Architecture.

[BibT_eX]

[DOI]

J. Circuits Syst. Comput., 2004

2003

High-speed VLSI architecture for parallel Reed-Solomon decoder.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2003

Performance evaluation and optimal design for FPGA-based digit-serial DSP functions.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2003

An Area-Efficient Euclidean Algorithm Block for Reed-Solomon Decoder.

[BibT_eX]

[DOI]

Proceedings of the 2003 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2003), 2003

2000

VLSI design of Reed-Solomon decoder architectures.

[BibT_eX]

[DOI]

Meng-Lin Yu

Leilei Song

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

1999

A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999

1998

FPGA Logic Block Architecture for Digit-Serial DSP Applications (Abstract).

[BibT_eX]

[DOI]

Sarvesh Shrivastava

Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, 1998

Digit-Serial DSP Library for Optimized FPGA Configuration.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998

1997

A New Low-Voltage Full Adder Circuit.

[BibT_eX]

[DOI]