Hyung Ki Lee

According to our database1, Hyung Ki Lee authored at least 9 papers between 1989 and 2007.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2007
NDIS-based virtual polling algorithm for IEEE 802.11b for guaranteeing the real-time requirements.
Comput. Stand. Interfaces, 2007

1996
HOPE: an efficient parallel fault simulator for synchronous sequential circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

1994
An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.
VLSI Design, 1994

1993
Fault simulation and test pattern generation for synchronous and asynchronous sequential circuits.
PhD thesis, 1993

New methods of improving parallel fault simulation in synchronous sequential circuits.
Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

1992
Comments on 'A method of fault simulation based on stem regions'.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

1991
An Efficient, Forward Fault Simulation Algorithm Based on the Parallel Pattern Single Fault Propagation.
Proceedings of the Proceedings IEEE International Test Conference 1991, 1991

1990
SOPRANO: An Efficient Automatic Test Pattern Generator for Stuck-Open Faults in CMOS Combinational Circuits.
Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989
Test Generation of Stuck-open Faults Using Stuck-at Test Sets in CMOS Combinational Circuits.
Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989


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