Iban Ayestaran

According to our database, Iban Ayestaran authored at least 7 papers between 2011 and 2017.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2017

A CAN Restbus HiL Elevator Simulator Based on Code Reuse and Device Para-Virtualization.

Carlos Fernando Nicolás, Iban Ayestaran, Tomaso Poggi, Goiuria Sagardui, Jose-Maria Martin

Proceedings of the 20th IEEE International Symposium on Real-Time Distributed Computing, 2017

2016

Model-Based Development of an FPGA Encoder Simulator for Real-Time Testing of Elevator Controllers.

Carlos Fernando Nicolás, Iban Ayestaran, Imanol Martinez, Patricia Franco

Proceedings of the 19th IEEE International Symposium on Real-Time Distributed Computing, 2016

2014

A Simulated Fault Injection Framework for Time-Triggered Safety-Critical Embedded Systems.

Iban Ayestaran, Carlos Fernando Nicolás, Jon Pérez, Asier Larrucea, Peter P. Puschner

Proceedings of the Computer Safety, Reliability, and Security, 2014

Modeling logical execution time based safety-critical embedded systems in SystemC.

Iban Ayestaran, Carlos F. Nicolás, Jon Pérez, Peter P. Puschner

Proceedings of the 3rd Mediterranean Conference on Embedded Computing, 2014

Modeling and Simulated Fault Injection for Time-Triggered Safety-Critical Embedded Systems.

Iban Ayestaran, Carlos Fernando Nicolás, Jon Pérez, Asier Larrucea, Peter P. Puschner

Proceedings of the 17th IEEE International Symposium on Object/Component/Service-Oriented Real-Time Distributed Computing, 2014

A novel modeling framework for time-triggered safety-critical embedded systems.

Iban Ayestaran, Carlos Fernando Nicolás, Jon Pérez, Asier Larrucea, Peter P. Puschner

Proceedings of the 2014 Forum on Specification and Design Languages, 2014

2011

Modeling time-triggered real-time control systems using executable time-triggered model (E-TTM) and systemC-AMS.

Jon Pérez, Roman Obermaisser, Carlos Fernando Nicolás, Iban Ayestaran

Comput. Syst. Sci. Eng., 2011