Ignacio Herrera-Alzu

According to our database, Ignacio Herrera-Alzu authored at least 3 papers between 2008 and 2015.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2015

A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs.

Ignacio Herrera-Alzu, Marisa López-Vallejo, C. Gil Soriano

Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2011

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs.

Ignacio Herrera-Alzu, Marisa López-Vallejo

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

2008

Experimental methodology for power characterization of FPGAs.

Ignacio Herrera-Alzu, Miguel Angel Sánchez, Marisa López-Vallejo, Pedro Echeverría

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008