Marisa López-Vallejo

According to our database1, Marisa López-Vallejo authored at least 72 papers between 1996 and 2019.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Bibliography

2019
A low power RFID based energy harvesting temperature resilient CMOS-only reference voltage.
Integr., 2019

Temperature-aware writing architecture for multilevel memristive cells.
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019

A 365mV, 13nW CMOS-only energy harvested reference voltage for RFID applications in 40nm technology.
Proceedings of the XXXIV Conference on Design of Circuits and Integrated Systems, 2019

2018
Guest Editorial: Special Section on Fast Fourier Transform (FFT) Hardware Implementations.
Signal Processing Systems, 2018

Auto-Erasable RRAM Architecture Secured Against Physical and Firmware Attacks.
IEEE Trans. on Circuits and Systems, 2018

A Temperature Variation Tolerant CMOS-Only Voltage Reference for RFID Applications.
Proceedings of the 28th International Symposium on Power and Timing Modeling, 2018

Performance-oriented Implementation of Hilbert Filters on FPGAs.
Proceedings of the Conference on Design of Circuits and Integrated Systems, 2018

2017
A 4096-Point Radix-4 Memory-Based FFT Using DSP Slices.
IEEE Trans. VLSI Syst., 2017

Reconfigurable Writing Architecture for Reliable RRAM Operation in Wide Temperature Ranges.
IEEE Trans. VLSI Syst., 2017

Advanced integration of variability and degradation in RRAM SPICE compact models.
Proceedings of the 14th International Conference on Synthesis, 2017

2016
A Performance Study of CUDA UVM versus Manual Optimizations in a Real-World Setup: Application to a Monte Carlo Wave-Particle Event-Based Interaction Model.
IEEE Trans. Parallel Distrib. Syst., 2016

SPICE Compact Modeling of Bipolar/Unipolar Memristor Switching Governed by Electrical Thresholds.
IEEE Trans. on Circuits and Systems, 2016

Reliable design methodology: The combined effect of radiation, variability and temperature.
Proceedings of the 13th International Conference on Synthesis, 2016

A temperature-independent PUF with a configurable duty cycle of CMOS ring oscillators.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

2015
Implementation of a Real-Time Spectrum Analyzer on FPGA Platforms.
IEEE Trans. Instrumentation and Measurement, 2015

An In-Depth Analysis of Ring Oscillators: Exploiting Their Configurable Duty-Cycle.
IEEE Trans. on Circuits and Systems, 2015

Real-time low-complexity automatic modulation classifier for pulsed radar signals.
IEEE Trans. Aerospace and Electronic Systems, 2015

Evolution of radiation-induced soft errors in FinFET SRAMs under process variations beyond 22nm.
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A thermal adaptive scheme for reliable write operation on RRAM based architectures.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

A Dual-Layer Fault Manager for systems based on Xilinx Virtex FPGAs.
Proceedings of the 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2015

2014
A Self-Timed Multipurpose Delay Sensor for Field Programmable Gate Arrays (FPGAs).
Sensors, 2014

2013
High Performance FPGA-oriented Mersenne Twister Uniform Random Number Generator.
Signal Processing Systems, 2013

Floating-Point Exponentiation Units for Reconfigurable Computing.
TRETS, 2013

A 0.0016 mm2 0.64 nJ Leakage-Based CMOS Temperature Sensor.
Sensors, 2013

A low power 6t-SRAM using negative bit-line for variability tolerance beyond 22nm node.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

A Low-Area Reference-Free Power Supply Sensor.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012
Hardware Reuse Improvement through the Domain Specific Language dHDL.
Proceedings of the 10th IEEE International Symposium on Parallel and Distributed Processing with Applications, 2012

A monitoring infrastructure for FPGA self-awareness and dynamic adaptation.
Proceedings of the 19th IEEE International Conference on Electronics, Circuits and Systems, 2012

Improving Hardware Reuse through XML-based Interface Encapsulation.
Proceedings of the 17th IEEE International Conference on Engineering of Complex Computer Systems, 2012

2011
Customizing floating-point units for FPGAs: Area-performance-standard trade-offs.
Microprocess. Microsystems, 2011

Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Real time FPGA implementation of an automatic modulation classifier for electronic warfare applications.
Proceedings of the 19th European Signal Processing Conference, 2011

On-chip Monitoring: A Light-Weight Interconnection Network Approach.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
Thermal analysis and modeling of embedded processors.
Comput. Electr. Eng., 2010

2009
Exploring performance-power trade-offs for look-up tables in SRAM-based FPGAs.
Proceedings of the 16th IEEE International Conference on Electronics, 2009

SoC Communication Architectures: From Interconnection Buses to Packet-Switched NoCs.
Proceedings of the Embedded Systems Design and Verification, 2009

2008
Power Considerations in Banked CAMs: A Leakage Reduction Approach.
VLSI Design, 2008

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.
Integr., 2008

A hardware mechanism to reduce the energy consumption of the register file of in-order architectures.
IJES, 2008

Experimental methodology for power characterization of FPGAs.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

Variance reduction techniques for Monte Carlo simulations. A parameterizable FPGA approach.
Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A Web-Based Environment Providing Remote Access To FPGA Platforms For Teaching Digital Hardware Design.
Proceedings of the IADIS International Conference e-Learning 2008, 2008

Designing Highly Parameterized Hardware using xHdl.
Proceedings of the Forum on specification and Design Languages, 2008

An FPGA run-time parameterisable Log-Normal Random Number Generator.
Proceedings of the Reconfigurable Computing: Architectures, 2008

2007
Energy-aware compilation and hardware design for VLIW embedded systems.
IJES, 2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Leakage-based On-Chip Thermal Sensor for CMOS Technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Joint Source-Channel Decoding ASIP Architecture for Sensor Networks.
Proceedings of the Embedded Software and Systems, [Third] International Conference, 2007

Thermal Characterization and Thermal Management in Processor-Based Systems.
Proceedings of the Power-aware Computing Systems, 21.01. - 26.01.2007, 2007

2006
Target Independent Thermal Modeling for Embedded Processors.
Proceedings of the International Symposium on Industrial Embedded Systems, 2006

Compiler-Driven Leakage Energy Reduction in Banked Register Files.
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Leakage Energy Reduction in Banked Content Addressable Memories.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Analysis of the Thermal Impact of Source-Code Transformations in Embedded-Processors.
Proceedings of the 13th IEEE International Conference on Electronics, 2006

Automated design space exploration of FPGA-based FFT architectures based on area and power estimation.
Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

New Schemes in Clustered VLIW Processors Applied to Turbo Decoding.
Proceedings of the 2006 IEEE International Conference on Application-Specific Systems, 2006

2005
State-of-the-Art SoC Communication Architectures.
Proceedings of the Embedded Systems Handbook., 2005

Integrating functional and power simulation in embedded systems design.
J. Embedded Computing, 2005

Compiler-Driven Power Optimizations in the Register File of Processor-Based Systems.
Proceedings of the Power-aware Computing Systems, 3.-8. April 2005, 2005

2003
On the hardware-software partitioning problem: System modeling and partitioning techniques.
ACM Trans. Design Autom. Electr. Syst., 2003

Power-Aware Compilation for Register File Energy Reduction.
International Journal of Parallel Programming, 2003

A Unified Framework for Power-Aware Design of Embedded Systems.
Proceedings of the Integrated Circuit and System Design, 2003

An Efficient Hash Table Based Approach to Avoid State Space Explosion in History Driven Quasi-Static Scheduling.
Proceedings of the 2003 Design, 2003

Energy Aware Register File Implementation through Instruction Predecode.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

State Space Compression in History Driven Quasi-Static Scheduling.
Proceedings of the Embedded Software for SoC, 2003

2002
Block processing technique for low power turbo decoder design.
Proceedings of the 55th IEEE Vehicular Technology Conference, 2002

2001
ED68K. A design framework for the development of digital systems based on MC68000.
Proceedings of the Computers and Education. Towards an Interconnected Society, 2001

2000
Constraint-Driven System Partitioning.
Proceedings of the 2000 Design, 2000

1999
Hardware-Software Partitioning at the Knowledge Level.
Appl. Intell., 1999

1998
Hardware-Software Prototyping from LOTOS.
Design Autom. for Emb. Sys., 1998

Applying the Propose&Revise Strategy to the Hardware-Software Partitioning Problem.
Proceedings of the Methodology and Tools in Knowledge-Based Systems, 1998

A Knowledge-based System for Hardware-Software Partitioning.
Proceedings of the 1998 Design, 1998

1996
A Co-Design Methodology Based on Formal Specification and High-level Estimation.
Proceedings of the Forth International Workshop on Hardware/Software Codesign, 1996


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