Ik-Hyeon Jeon

According to our database, Ik-Hyeon Jeon authored at least 6 papers between 2024 and 2026.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of six.

2026

68.22 TOPS/W Full Boolean Logic Supportable eDRAM-Based Digital CIM with Energy-Efficient Input-Aware Toggle-Rate-Reduced Adder.

Ik-Hyeon Jeon, Ho-Sung Lee, Eun-Bi Koh, Junsung Park, Joo-Hyung Chae

Proceedings of the IEEE Custom Integrated Circuits Conference, 2026

2025

A Dual-Multiplication-Mode and Reconfigurable Digital Compute-in-Memory Macro Using Precharge-Controlled 4T1C eDRAM.

Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Eun-Bi Koh, Joo-Hyung Chae

IEEE Trans. Very Large Scale Integr. Syst., October, 2025

A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing.

Ik-Hyeon Jeon, Joo-Hyung Chae

IEEE Trans. Circuits Syst. I Regul. Pap., July, 2025

URcon: Unified and Reconfigurable Control and Verification Platform for Multi-Mode Customized eDRAM and SRAM Macros.

Ho-Sung Lee, Ik-Hyeon Jeon, Jiwon Lee, Hyeonjun Cheon, Joo-Hyung Chae

IEEE Access, 2025

2024

Design of 16-Kb 6T SRAM Supporting Wide Parallel Data Access for Enhanced Computation Speed.

Jiwon Lee, Hyeonjun Cheon, Ho-Sung Lee, Ik-Hyeon Jeon, Joo-Hyung Chae

Proceedings of the 21st International SoC Design Conference, 2024

A 16-Kb 1T1C DRAM Supporting Conventional and Compute-in-Memory Access Modes.

Hyeonjun Cheon, Ho-Sung Lee, Jiwon Lee, Ik-Hyeon Jeon, Joo-Hyung Chae

Proceedings of the 21st International SoC Design Conference, 2024