Ilija Hadzic

Orcid: 0000-0002-7996-6398

According to our database1, Ilija Hadzic authored at least 21 papers between 1997 and 2023.

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Bibliography

2023
SACPlanner: Real-World Collision Avoidance with a Soft Actor Critic Local Planner and Polar State Representations.
Proceedings of the IEEE International Conference on Robotics and Automation, 2023

2021
Safe Predictive Control of Four-Wheel Mobile Robot with Independent Steering and Drive.
Proceedings of the 2021 American Control Conference, 2021

2019
Server Placement and Selection for Edge Computing in the ePC.
IEEE Trans. Serv. Comput., 2019

2017
Edge computing in the ePC: a reality check.
Proceedings of the Second ACM/IEEE Symposium on Edge Computing, San Jose / Silicon Valley, 2017

2016
Low-Level Frame-Buffer Scraping for GPUs in the Cloud.
Proceedings of the IEEE International Symposium on Multimedia, 2016

Building Media-Rich Cloud Services from Network-Attached I/O Devices.
Proceedings of the 4th IEEE International Conference on Future Internet of Things and Cloud, 2016

2013
A Simple Desktop Compression and Streaming System.
Proceedings of the 2013 IEEE International Symposium on Multimedia, 2013

2012
3D Rendering in the Cloud.
Bell Labs Tech. J., 2012

2011
A Synchronization Algorithm for Packet MANs.
IEEE Trans. Commun., 2011

2010
Nonuniform linear regression with block-wise sample-minimum preprocessing.
IEEE Trans. Signal Process., 2010

Improving IEEE 1588v2 clock performance through controlled packet departures.
IEEE Commun. Lett., 2010

A simple analysis of linear regression with sample-minimum Erlang variates.
Proceedings of the IEEE International Conference on Acoustics, 2010

2009
Synthesis and Optimization of Pipelined Packet Processors.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

2006
Synthesis of high-performance packet processing pipelines.
Proceedings of the 43rd Design Automation Conference, 2006

2005
High-performance synchronization for circuit emulation in an Ethernet MAN.
J. Commun. Networks, 2005

An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

2003
Balancing performance and flexibility with hardware support for network architectures.
ACM Trans. Comput. Syst., 2003

2001
Hierarchical MAC address space in public Ethernet networks.
Proceedings of the Global Telecommunications Conference, 2001

1999
FPGA Viruses.
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1998
Protocol boosters: applying programmability to network infrastructures.
IEEE Commun. Mag., 1998

1997
P4: A platform for FPGA implementation of protocol boosters.
Proceedings of the Field-Programmable Logic and Applications, 7th International Workshop, 1997


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