Ilker Hamzaoglu
Orcid: 0000-0002-6491-689X
According to our database1,
Ilker Hamzaoglu
authored at least 96 papers
between 1997 and 2024.
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Bibliography
2024
J. Real Time Image Process., April, 2024
2023
An efficient algorithm for disparity map compression based on spatial correlations and its low-cost hardware architecture.
Integr., November, 2023
2022
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
Proceedings of the IEEE International Conference on Consumer Electronics, 2022
2021
Approximate Versatile Video Coding Fractional Interpolation Filters and Their Hardware Implementations.
IEEE Trans. Consumer Electron., 2021
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
Proceedings of the IEEE International Conference on Consumer Electronics, 2021
2020
Proceedings of the 2020 IEEE International Conference on Consumer Electronics (ICCE), 2020
A Novel Approximate Constant Multiplier and HEVC Discrete Cosine Transform Case Study.
Proceedings of the 10th IEEE International Conference on Consumer Electronics, 2020
Proceedings of the 23rd Euromicro Conference on Digital System Design, 2020
2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
Proceedings of the 22nd Euromicro Conference on Digital System Design, 2019
2018
Approximate HEVC Fractional Interpolation Filters and Their Hardware Implementations.
IEEE Trans. Consumer Electron., 2018
J. Real Time Image Process., 2018
J. Real Time Image Process., 2018
An HEVC fractional interpolation hardware using memory based constant multiplication.
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018
Proceedings of the 21st Euromicro Conference on Digital System Design, 2018
Proceedings of the 2018 Conference on Design and Architectures for Signal and Image Processing, 2018
2017
IEEE Trans. Consumer Electron., 2017
Low complexity 2D adaptive image processing algorithm and its hardware implementation.
IEEE Trans. Consumer Electron., 2017
IEEE Trans. Consumer Electron., 2017
IEEE Trans. Consumer Electron., 2017
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017
Pixel correlation based computation and energy reduction techniques for HEVC fractional interpolation.
Proceedings of the 7th IEEE International Conference on Consumer Electronics - Berlin, 2017
2016
IEEE Trans. Consumer Electron., 2016
Low complexity HEVC sub-pixel motion estimation technique and its hardware implementation.
Proceedings of the IEEE 6th International Conference on Consumer Electronics - Berlin, 2016
Proceedings of the IEEE 6th International Conference on Consumer Electronics - Berlin, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016
2015
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015
Proceedings of the 2015 Conference on Design and Architectures for Signal and Image Processing, 2015
2014
IEEE Trans. Consumer Electron., 2014
Proceedings of the 2014 IEEE International Conference on Image Processing, 2014
Proceedings of the IEEE Fourth International Conference on Consumer Electronics Berlin, 2014
Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014
2013
IEEE Trans. Consumer Electron., 2013
A high performance and low energy hardware for intra prediction with Template Matching.
Proceedings of the 21st IEEE/IFIP International Conference on VLSI and System-on-Chip, 2013
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013
Proceedings of the IEEE Third International Conference on Consumer Electronics, 2013
2012
IEEE Trans. Consumer Electron., 2012
Microprocess. Microsystems, 2012
Microprocess. Microsystems, 2012
A high performance and low energy intra prediction hardware for High Efficiency Video Coding.
Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012
Proceedings of the 2012 Conference on Design and Architectures for Signal and Image Processing, 2012
2011
An adaptive true motion estimation algorithm for frame rate conversion of high definition video and its hardware implementations.
IEEE Trans. Consumer Electron., 2011
IEEE Trans. Consumer Electron., 2011
IEEE Trans. Consumer Electron., 2011
Proceedings of the 18th IEEE International Conference on Image Processing, 2011
Proceedings of the International Conference on Field Programmable Logic and Applications, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
High performance hardware architectures for one bit transform based single and multiple reference frame motion estimation.
IEEE Trans. Consumer Electron., 2010
Pixel similarity based computation and power reduction technique for H.264 intra prediction.
IEEE Trans. Consumer Electron., 2010
Proceedings of the 18th IEEE/IFIP VLSI-SoC 2010, 2010
Recursive Dynamically Variable Step Search Motion Estimation Algorithm for High Definition Video.
Proceedings of the 20th International Conference on Pattern Recognition, 2010
An Adaptive True Motion Estimation Algorithm for Frame Rate Conversion of High Definition Video.
Proceedings of the 20th International Conference on Pattern Recognition, 2010
Computation Reduction Techniques for Vector Median Filtering and their Hardware Implementation.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010
A reconfigurable hardware for one bit transform based multiple reference frame Motion Estimation.
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation.
IEEE Trans. Consumer Electron., 2009
High performance hardware architectures for one bit transform based motion estimation.
IEEE Trans. Consumer Electron., 2009
IEEE Signal Process. Lett., 2009
Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009
A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
IEEE Trans. Consumer Electron., 2008
A novel computational complexity and power reduction technique for H.264 intra prediction.
IEEE Trans. Consumer Electron., 2008
IEEE Trans. Consumer Electron., 2008
2007
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation.
Proceedings of the IFIP VLSI-SoC 2006, 2006
Proceedings of the First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 2006
2005
A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
A high performance and low cost hardware architecture for H.264 transform and quantization algorithms.
Proceedings of the 13th European Signal Processing Conference, 2005
Proceedings of the 13th European Signal Processing Conference, 2005
2000
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000
Proceedings of the 18th IEEE VLSI Test Symposium (VTS 2000), 30 April, 2000
Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000
1999
Test Pattern Generation and Test Application Time Reduction Algorithms for VLSI Circuits
PhD thesis, 1999
Proceedings of the Digest of Papers: FTCS-29, 1999
1998
Proceedings of the Proceedings IEEE International Test Conference 1998, 1998
1997
Proceedings of the Third International Conference on Knowledge Discovery and Data Mining (KDD-97), 1997
Proceedings of the AMIA 1997, 1997