Halil Kukner

According to our database1, Halil Kukner authored at least 18 papers between 2009 and 2022.

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Bibliography

2022
RISC-V Processor Trace Encoder with Multiple Instructions Retirement Support.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022

2017
Integral Impact of BTI, PVT Variation, and Workload on SRAM Sense Amplifier.
IEEE Trans. Very Large Scale Integr. Syst., 2017

2015
Comparison of NBTI aging on adder architectures and ring oscillators in the downscaling technology nodes.
Microprocess. Microsystems, 2015

Integral impact of BTI and voltage temperature variation on SRAM sense amplifier.
Proceedings of the 33rd IEEE VLSI Test Symposium, 2015

The defect-centric perspective of device and circuit reliability - From individual defects to circuits.
Proceedings of the 45th European Solid State Device Research Conference, 2015

2014
Degradation analysis of datapath logic subblocks under NBTI aging in FinFET technology.
Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Modelling and mitigation of time-zero variability in sub-16nm finfet-based STT-MRAM memories.
Proceedings of the Great Lakes Symposium on VLSI 2014, GLSVLSI '14, Houston, TX, USA - May 21, 2014

NBTI Aging on 32-Bit Adders in the Downscaling Planar FET Technology Nodes.
Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Bias Temperature Instability analysis of FinFET based SRAM cells.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013
Impact of duty factor, stress stimuli, gate and drive strength on gate delay degradation with an atomistic trap-based BTI model.
Microprocess. Microsystems, 2013

Impact of partial resistive defects and Bias Temperature Instability on SRAM decoder reliablity.
Proceedings of the 8th International Design and Test Symposium, 2013

Bias temperature instability analysis in SRAM decoder.
Proceedings of the 18th IEEE European Test Symposium, 2013

2012
Impact of Duty Factor, Stress Stimuli, and Gate Drive Strength on Gate Delay Degradation with an Atomistic Trap-Based BTI Model.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012

Incorporating parameter variations in BTI impact on nano-scale logical gates analysis.
Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

BTI impact on logical gates in nano-scale CMOS technology.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

2011
Generic, orthogonal and low-cost March Element based memory BIST.
Proceedings of the 2011 IEEE International Test Conference, 2011

2009
Dynamically variable step search motion estimation algorithm and a dynamically reconfigurable hardware for its implementation.
IEEE Trans. Consumer Electron., 2009

A high performance reconfigurable Motion Estimation hardware architecture.
Proceedings of the Design, Automation and Test in Europe, 2009


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