Ireneusz Janiszewski

According to our database, Ireneusz Janiszewski authored at least 4 papers between 2001 and 2004.

Collaborative distances:

• Dijkstra number of six.
• Erdős number of six.

2004

FPGA-efficient phase-to-I/Q architecture.

Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe

Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

FPGA-Efficient Hybrid LUT/CORDIC Architecture.

Ireneusz Janiszewski, Hermann Meuth, Bernhard Hoppe

Proceedings of the Field Programmable Logic and Application, 2004

2002

Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators.

Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth

Proceedings of the 16^th European Simulation Multiconference: Modelling and Simulation 2002, 2002

2001

VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers.

Ireneusz Janiszewski, Bernhard Hoppe, Hermann Meuth

Proceedings of the 38th Design Automation Conference, 2001