Bernhard Hoppe

According to our database1, Bernhard Hoppe authored at least 10 papers between 1990 and 2012.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of five.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2012
Opening a M. Sc. in Electrical Engineering for non-traditional Students.
Int. J. Adv. Corp. Learn., 2012

2007
A Multichannel Digital Real-Time Correlator as Single FPGA Implementation.
Proceedings of the 15th International Conference on Digital Signal Processing, 2007

A FPGA Optimised Digital Real-Time Mutichannel Correlator Architecture.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2004
FPGA-efficient phase-to-I/Q architecture.
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004

FPGA-Efficient Hybrid LUT/CORDIC Architecture.
Proceedings of the Field Programmable Logic and Application, 2004

2002
Modelling and Simulation in the Design Flow for Numerically Controlled Oscillators.
Proceedings of the 16<sup>th</sup> European Simulation Multiconference: Modelling and Simulation 2002, 2002

2001
VHDL-Based Design and Design Methodology for Reusable High Performance Direct Digital Frequency Synthesizers.
Proceedings of the 38th Design Automation Conference, 2001

1999
A single chip 200 MHz digital correlation system for laser spectroscopy with 512 correlation channels.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

1990
Optimization of high-speed CMOS logic circuits with analytical models for signal delay, chip area, and dynamic power dissipation.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1990

Transmission gate delay models for circuit optimization.
Proceedings of the European Design Automation Conference, 1990


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