Itai Jaeger

According to our database1, Itai Jaeger authored at least 9 papers between 2002 and 2007.

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Bibliography

2007
Constraint-Based Random Stimuli Generation for Hardware Verification.
AI Mag., 2007

Intelligent Interleaving of Scenarios: A Novel Approach to System Level Test Generation.
Proceedings of the 44th Design Automation Conference, 2007

A Framework for the Validation of Processor Architecture Compliance.
Proceedings of the 44th Design Automation Conference, 2007

2006
Harnessing Machine Learning to Improve the Success Rate of Stimuli Generation.
IEEE Trans. Computers, 2006

Addressing Test Generation Challenges for Configurable Processor Verification.
Proceedings of the Eleventh Annual IEEE International High-Level Design Validation and Test Workshop 2006, 2006

2005
Path-Based System Level Stimuli Generation.
Proceedings of the Hardware and Software Verification and Testing, 2005

Reuse in system-level stimuli-generation.
Proceedings of the Tenth IEEE International High-Level Design Validation and Test Workshop 2005, Napa Valley, CA, USA, November 30, 2005

2004
Quality Improvement Methods for System-Level Stimuli Generation.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2002
X-Gen: a random test-case generator for systems and SoCs.
Proceedings of the Seventh IEEE International High-Level Design Validation and Test Workshop 2002, 2002


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