Iyad Ouaiss

According to our database1, Iyad Ouaiss authored at least 16 papers between 1998 and 2020.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2020
Toward an Improvement of Engineering Teaming Skills Through an In-House Professionalism Course.
IEEE Trans. Educ., 2020

2015
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations.
J. Circuits Syst. Comput., 2015

2011
Priority-Driven Area Optimization in High-Level Synthesis.
J. Circuits Syst. Comput., 2011

A Novel Register-Binding Approach to Reduce Spurious Switching Activity in High-Level Synthesis.
J. Circuits Syst. Comput., 2011

2010
A novel pseudorandom noise and band jammer generator using a composite sinusoidal function.
IEEE Trans. Signal Process., 2010

Deadline-based connection setup in wavelength-routed WDM networks.
Comput. Networks, 2010

2005
Optimizing register binding in FPGAs using simulated annealing.
Proceedings of the 2005 International Conference on Reconfigurable Computing and FPGAs, 2005

2004
Storage Allocation for Diverse FPGA Memory Specifications.
Proceedings of the Field Programmable Logic and Application, 2004

Register Binding for FPGAs with Embedded Memory.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

2001
Global memory mapping for FPGA-based reconfigurable systems.
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001

Memory Synthesis for FPGA-Based Reconfigurable Computers.
Proceedings of the Field-Programmable Logic and Applications, 2001

Hierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000
Efficient Resource Arbitration in Reconfigurable Computing Environments.
Proceedings of the 2000 Design, 2000

1999
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications.
Proceedings of the 36th Conference on Design Automation, 1999

1998
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998

An Effective Design System for Dynamically Reconfigurable Architectures.
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998


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