Ranga Vemuri
Orcid: 0000-0002-4903-2746Affiliations:
- University of Cincinnati, OH, USA
According to our database1,
Ranga Vemuri
authored at least 270 papers
between 1978 and 2024.
Collaborative distances:
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Bibliography
2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
Proceedings of the 37th International Conference on VLSI Design and 23rd International Conference on Embedded Systems, 2024
2023
IEEE Access, 2023
Word-Level Structure Identification In FPGA Designs Using Cell Proximity Information.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Mutation Analysis and Model Checking Guided Test Generation for SoC Run-Time Monitors.
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
Proceedings of the 36th International Conference on VLSI Design and 2023 22nd International Conference on Embedded Systems, 2023
RELUT-GNN: Reverse Engineering Data Path Elements From LUT Netlists Using Graph Neural Networks.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Split Manufacturing Based Secure Hardware Design by BEOL Signal Selection In High Level Synthesis.
Proceedings of the 66th IEEE International Midwest Symposium on Circuits and Systems, 2023
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2023
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
Attributed Graph Transformation for Generating Synthetic Benchmarks for Hardware Security.
Proceedings of the 24th International Symposium on Quality Electronic Design, 2023
2022
FPGA-Based Stochastic Local Search Satisfiability Solvers Exploiting High Bandwidth Memory.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
FPGA Acceleration of a Stochastic Local Search Portfolio Solver for Boolean Satisfiability.
Proceedings of the 65th IEEE International Midwest Symposium on Circuits and Systems, 2022
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022
Analysis of the Satisfiability Attack Against Logic Encryption Using Synthetic Benchmarks.
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2022
Proceedings of the IEEE 40th International Conference on Computer Design, 2022
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022
S*FSMs for Reduced Information Leakage: Power Side Channel Protection Through Secure Encoding.
Behavioral Synthesis for Hardware Security, 2022
Behavioral Synthesis for Hardware Security, 2022
2021
Educating the Next Generation of Cybersecurity Defenders at the University of Cincinnati.
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Proceedings of the 64th IEEE International Midwest Symposium on Circuits and Systems, 2021
Security Capsules: An Architecture for Post-Silicon Security Assertion Validation for Systems-on-Chip.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2021
Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2021
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
2020
Proceedings of the 33rd International Conference on VLSI Design and 19th International Conference on Embedded Systems, 2020
Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020
Proceedings of the 21st International Symposium on Quality Electronic Design, 2020
2019
IET Comput. Digit. Tech., 2019
J. Electron. Test., 2019
A State Encoding Methodology for Side-Channel Security vs. Power Trade-off Exploration.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Non-Invasive Reverse Engineering of Finite State Machines Using Power Analysis and Boolean Satisfiability.
Proceedings of the 62nd IEEE International Midwest Symposium on Circuits and Systems, 2019
Proceedings of the 2019 IEEE Computer Society Annual Symposium on VLSI, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the 20th International Symposium on Quality Electronic Design, 2019
Proceedings of the Internet of Things. A Confluence of Many Disciplines, 2019
Exploiting Proximity Information in a Satisfiability Based Attack Against Split Manufactured Circuits.
Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2019
2018
Combined Inference and Satisfiability Based Methods for Complete Signal Restoration in Post-Silicon Validation.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Proceedings of the IEEE International Conference on Consumer Electronics, 2018
Reverse Engineering of Split Manufactured Sequential Circuits Using Satisfiability Checking.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018
Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, 2018
Improving the Security of Split Manufacturing Using a Novel BEOL Signal Selection Method.
Proceedings of the 2018 on Great Lakes Symposium on VLSI, 2018
2017
Proceedings of the 2017 IEEE International Conference on Computer Design, 2017
2016
Proceedings of the 34th IEEE International Conference on Computer Design, 2016
2014
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014
2013
Design automation flow for voltage adaptive optimum granularity LITHE for sequential circuits.
Proceedings of the 2013 IEEE International SOC Conference, Erlangen, Germany, 2013
Proceedings of the IEEE 56th International Midwest Symposium on Circuits and Systems, 2013
2012
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012
SDMLp: On the use of complementary Pass transistor Logic for design of DPA resistant circuits.
Proceedings of the 2012 IEEE International Symposium on Hardware-Oriented Security and Trust, 2012
Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Aggressive Runtime Leakage Control Through Adaptive Light-Weight V<sub>th</sub> Hopping With Temperature and Process Variation.
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, 2011
2010
J. Low Power Electron., 2010
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the Annual IEEE International SoC Conference, SoCC 2010, 2010
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010
Current shaping and multi-thread activation for fast and reliable power mode transition in multicore designs.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
Stretching the limit of microarchitectural level leakage control with Adaptive Light-Weight Vth Hopping.
Proceedings of the 2010 International Conference on Computer-Aided Design, 2010
2009
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Fuzzy Logic Based Guidance to Graph Grammar Framework for Automated Analog Circuit Design.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Variation-Aware Macromodeling and Synthesis of Analog Circuits Using Spline Center and Range Method and Dynamically Reduced Design Space.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Accurate estimation of vector dependent leakage power in the presence of process variations.
Proceedings of the 27th International Conference on Computer Design, 2009
Proceedings of the 2009 International Conference on Computer-Aided Design, 2009
A methodology for application-specific NoC architecture generation in a dynamic task structure environment.
Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009
Selective light Vth hopping (SLITH): Bridging the gap between runtime dynamic and leakage.
Proceedings of the Design, Automation and Test in Europe, 2009
Proceedings of the Design, Automation and Test in Europe, 2009
2008
Reduced Complementary Dynamic and Differential Logic: A CMOS Logic Style for DPA-Resistant Secure IC Design.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Proceedings of the 2008 International Symposium on Low Power Electronics and Design, 2008
ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
Run-time Active Leakage Reduction by power gating and reverse body biasing: An eNERGY vIEW.
Proceedings of the 26th International Conference on Computer Design, 2008
Proceedings of the 2008 International Conference on Computer-Aided Design, 2008
A layout-aware analog synthesis procedure inclusive of dynamic module geometry selection.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
Proceedings of the Applications of Evolutionary Computing, 2008
Proceedings of the Design, Automation and Test in Europe, 2008
Proceedings of the 45th Design Automation Conference, 2008
2007
Efficient Symbolic Sensitivity based Parasitic-Inclusive Optimization in Layout Aware Analog Circuit Synthesis.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A Force-directed Approach for Fast Generation of Efficient Multi-Port NoC Architectures.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
Power invariant secure IC design methodology using reduced complementary dynamic and differential logic.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Accurate Performance Estimation using Circuit Matrix Models in Analog Circuit Synthesis.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Regression based circuit matrix models for accurate performance estimation of analog circuits.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Process Variation and NBTI Tolerant Standard Cells to Improve Parametric Yield and Lifetime of ICs.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Process Variation Tolerant Standard Cell Library Development Using Reduced Dimension Statistical Modeling and Optimization Techniques.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007
Multicasting based topology generation and core mapping for a power efficient networks-on-chip.
Proceedings of the 2007 International Symposium on Low Power Electronics and Design, 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the Sixth International Conference on Machine Learning and Applications, 2007
Power variations of multi-port routers in an application-specific NoC design : A case study.
Proceedings of the 25th International Conference on Computer Design, 2007
2006
IEEE Trans. Very Large Scale Integr. Syst., 2006
Hierarchical constraint transformation based on genetic optimization for analog system synthesis.
Integr., 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Efficient Analog Performance Macromodeling via Sequential Design Space Decomposition.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Symbolic Time-Domain Behavioral and Performance Modeling of Linear Analog Circuits Using an Efficient Symbolic Newton-Iteration Algorithm for Pole Extraction.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2006
Exact hierarchical symbolic analysis of large analog networks using a general interconnection template.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 2006 International Conference on Computer-Aided Design, 2006
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006
Multi2 Router: A Novel Multi Local Port Router Architecture with Broadcast Facility for FPGA-Based Networks-on-Chip.
Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006
Efficient temperature-dependent symbolic sensitivity analysis and symbolic performance evaluation in analog circuit synthesis.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs.
Proceedings of the Conference on Design, Automation and Test in Europe, 2006
2005
Int. J. Embed. Syst., 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
An Active Learning Scheme Using Support Vector Machines for Analog Circuit Feasibility Classification.
Proceedings of the 18th International Conference on VLSI Design (VLSI Design 2005), 2005
Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis Based on Element-Coefficient Diagrams.
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
Battery-Efficient Task Execution on Reconfigurable Computing Platforms with Multiple Processing Units.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005
Hierarchical performance macromodels of feasible regions for synthesis of analog and RF circuits.
Proceedings of the 2005 International Conference on Computer-Aided Design, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Accuracy driven performance macromodeling of feasible regions during synthesis of analog circuits.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005
Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005
Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005
An Iterative Algorithm for Battery-Aware Task Scheduling on Portable Computing Platforms.
Proceedings of the 2005 Design, 2005
Proceedings of the 2005 Design, 2005
Inductive and Capacitive Coupling Aware Routing Methodology Driven by a Higher Order RLCK Moment Metric.
Proceedings of the 2005 Design, 2005
Multi-Placement Structures for Fast and Optimized Placement in Analog Circuit Synthesis.
Proceedings of the 2005 Design, 2005
Proceedings of the 42nd Design Automation Conference, 2005
Efficient symbolic sensitivity analysis of analog circuits using element-coefficient diagrams.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
An error-driven adaptive grid refinement algorithm for automatic generation of analog circuit performance macromodels.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005
2004
A two-layer library-based approach to synthesis of analog systems from VHDL-AMS specifications.
ACM Trans. Design Autom. Electr. Syst., 2004
Proceedings of the Proceedings 2004 IEEE International SOC Conference, 2004
Forward-Looking Macro Generation and Relational Placement During High Level Synthesis to FPGAs.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004
Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems.
Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004
Adaptive sampling and modeling of analog circuit performance parameters with pseudo-cubic splines.
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
Proceedings of the 2004 International Conference on Computer-Aided Design, 2004
A high level language for pre-layout extraction in parasite-aware analog circuit synthesis.
Proceedings of the 14th ACM Great Lakes Symposium on VLSI 2004, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the Field Programmable Logic and Application, 2004
A Power-Performance Trade-off Methodology for Portable Reconfigurable Platforms.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004
A Portable Face Recognition System Using Reconfigurable Hardware.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004
Area Fragmentation in Reconfigurable Operating Systems.
Proceedings of the International Conference on Engineering of Reconfigurable Systems and Algorithms, 2004
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models.
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 2004 Design, 2004
Proceedings of the 41th Design Automation Conference, 2004
Proceedings of the 41th Design Automation Conference, 2004
A Design Methodology for Self-Timed Event Logic Pipelines.
Proceedings of the International Conference on Embedded Systems and Applications, 2004
2003
Extraction and use of neural network models in automated synthesis of operational amplifiers.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Exploration-based high-level synthesis of linear analog systems operating at low/medium frequencies.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
Behavioral modeling for high-level synthesis of analog and mixed-signal systems from VHDL-AMS.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003
A Fast Macro Based Compilation Methodology for Partially Reconfigurable FPGA Designs.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Adaptive Sampling and Modeling of Analog Circuit Performance Parameters.
Proceedings of the IFIP VLSI-SoC 2003, 2003
MSL: A High-Level Language for Parameterized Analog and Mixed Signal Layout Generators.
Proceedings of the IFIP VLSI-SoC 2003, 2003
A Novel Synthesis Strategy Driven by Partial Evaluation Based Circuit Reduction for Application Specific DSP Circuits.
Proceedings of the 21st International Conference on Computer Design (ICCD 2003), 2003
2002
Hardware-software partitioning and pipelined scheduling of transformative applications.
IEEE Trans. Very Large Scale Integr. Syst., 2002
An efficient register optimization algorithm for high-level synthesis from hierarchical behavioral specifications.
ACM Trans. Design Autom. Electr. Syst., 2002
Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), 2002
Proceedings of the Field-Programmable Logic and Applications, 2002
Proceedings of the 2002 Design, 2002
2001
IEEE Trans. Very Large Scale Integr. Syst., 2001
Fine-grained and coarse-grained behavioral partitioning with effective utilization of memory and design space exploration for multi-FPGA architectures.
IEEE Trans. Very Large Scale Integr. Syst., 2001
Theorem Proving Guided Development of Formal Assertions in a Resource-Constrained Scheduler for High-Level Synthesis.
Formal Methods Syst. Des., 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001
Proceedings of the 2001 International Symposium on Circuits and Systems, 2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Proceedings of the 15th International Parallel & Distributed Processing Symposium (IPDPS-01), 2001
Proceedings of the Field-Programmable Logic and Applications, 2001
On the verification of synthesized designs using automatically generated transformational witnesses.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
A regularity-based hierarchical symbolic analysis method for large-scale analog networks.
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
Proceedings of the 38th Design Automation Conference, 2001
Integrated High-Level Synthesis and Power-Net Routing for Digital Design under Switching Noise Constraints.
Proceedings of the 38th Design Automation Conference, 2001
MAGELLAN: multiway hardware-software partitioning and scheduling for latency minimization of hierarchical control-dataflow task graphs.
Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001
Proceedings of the Correct Hardware Design and Verification Methods, 2001
Proceedings of the 19th Conference on Advanced Research in VLSI (ARVLSI 2001), 2001
2000
Design-Space Exploration for Block-Processing Based Temporal Partitioning of Run-Time Reconfigurable Systems.
J. VLSI Signal Process., 2000
Automated Correctness Condition Generation for Formal Verification of Synthesized RTL Designs.
Formal Methods Syst. Des., 2000
An Iterative Algorithm for Hardware-Software Partitioning, Hardware Design Space Exploration and Scheduling.
Des. Autom. Embed. Syst., 2000
Computer, 2000
A Technique for Dynamic High-Level Exploration During Behavioral-Partitioning for Multi-Device Architectures.
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the 13th International Conference on VLSI Design (VLSI Design 2000), 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
A heuristic technique for system-level architecture generation from signal-flow graph representations of analog systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
Behavioral Partitioning with Synthesis for Multi-FPGA Architectures under Interconnect, Area, and Latency Constraints.
Proceedings of the Parallel and Distributed Processing, 2000
An approach to high-level synthesis system validation using formally verified transformations.
Proceedings of the IEEE International High-Level Design Validation and Test Workshop 2000, 2000
Tightly Integrated Design Space Exploration with Spatial and Temporal Partitioning in SPARCS.
Proceedings of the Field-Programmable Logic and Applications, 2000
Proceedings of the 2000 Design, 2000
Proceedings of the 2000 Design, 2000
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement.
Proceedings of the 2000 Design, 2000
Proceedings of the 2000 Design, 2000
Towards a Specification Notation for High-Level Synthesis of Mixed-Signal and Analog Systems.
Proceedings of the 2000 IEEE/ACM International Workshop on Behavioral Modeling and Simulation, 2000
1999
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
Component Characterization and Constraint Transformation Based on Directed Intervals for Analog Synthesis.
Proceedings of the 12th International Conference on VLSI Design (VLSI Design 1999), 1999
An Iterative Algorithm for Partitioning and Scheduling of Area Constrained HW-SW Systems.
Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping (RSP 1999), 1999
A genetic approach to simultaneous parameter space exploration and constraint transformation in analog synthesis.
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
Proceedings of the Parallel and Distributed Processing, 1999
Integrated Block-Processing and Design-Space Exploration in Temporal Partitioning for RTR Architectures.
Proceedings of the Parallel and Distributed Processing, 1999
A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements.
Proceedings of the VLSI: Systems on a Chip, 1999
A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications.
Proceedings of the VLSI: Systems on a Chip, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the IEEE International Conference On Computer Design, 1999
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Hierarchical Scheduling in High Level Synthesis Using Resource Sharing Across Nested Loops.
Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999
Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999
Throughput Optimization with Design Space Exploration During Partitioning for Multi-FPGA Architectures.
Proceedings of the 1999 ACM/SIGDA Seventh International Symposium on Field Programmable Gate Arrays, 1999
Task-Level Partitioning and RTL Design Space Exploration for Multi-FPGA Architectures.
Proceedings of the 7th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '99), 1999
An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit Synthesis.
Proceedings of the 1999 Design, 1999
Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs.
Proceedings of the 1999 Design, 1999
Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured Designs.
Proceedings of the 1999 Design, 1999
A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog Systems.
Proceedings of the 1999 Design, 1999
Hierarchical Constraint Transformation Using Directed Interval Search for Analog System Synthesis.
Proceedings of the 1999 Design, 1999
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications.
Proceedings of the 36th Conference on Design Automation, 1999
Proceedings of the 36th Conference on Design Automation, 1999
Automatic Constraint Transformation with Integrated Parameter Space Exploration in Analog System Synthesis.
Proceedings of the 1999 Conference on Asia South Pacific Design Automation, 1999
1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
Proceedings of the 11th International Conference on VLSI Design (VLSI Design 1991), 1998
On the Effectiveness of Theorem Proving Guided Discovery of Formal Assertions for a Register Allocator in a High-Level Synthesis System.
Proceedings of the Theorem Proving in Higher Order Logics, 11th International Conference, 1998
Proceedings of the Ninth IEEE International Workshop on Rapid System Prototyping (RSP 1998), 1998
Proceedings of the 11th International Symposium on System Synthesis, 1998
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
An Integrated Partitioning and Synthesis System for Dynamically Reconfigurable Multi-FPGA Architectures.
Proceedings of the Parallel and Distributed Processing, 10 IPPS/SPDP'98 Workshops Held in Conjunction with the 12th International Parallel Processing Symposium and 9th Symposium on Parallel and Distributed Processing, Orlando, Florida, USA, March 30, 1998
Proceedings of the International Conference on Computer Design: VLSI in Computers and Processors, 1998
A Methodology for Automated Verification of Synthesized RTL Designs and Its Integration with a High-Level Synthesis Tool.
Proceedings of the Formal Methods in Computer-Aided Design, 1998
Proceedings of the 6th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM '98), 1998
Proceedings of the 1998 Design, 1998
Proceedings of the 1998 Design, 1998
RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns.
Proceedings of the Sixth International Workshop on Hardware/Software Codesign, 1998
1997
Proceedings of the 10th International Conference on VLSI Design (VLSI Design 1997), 1997
Dynamic Bounding of Successor Force Computations in the Force Directed List Scheduling Algorithms.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the European Design and Test Conference, 1997
Proceedings of the 34st Conference on Design Automation, 1997
A constructive method for data path area estimation during high-level VLSI synthesis.
Proceedings of the ASP-DAC '97 Asia and South Pacific Design Automation Conference, 1997
1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 9th International Conference on VLSI Design (VLSI Design 1996), 1996
Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996
Specification of Control Flow Properties for Verification of Synthesized VHDL Designs.
Proceedings of the Formal Methods in Computer-Aided Design, First International Conference, 1996
Proceedings of the conference on European design automation, 1996
Proceedings of the 1996 International Conference on Application-Specific Systems, 1996
1995
Generation of design verification tests from behavioral VHDL programs using path enumeration and constraint programming.
IEEE Trans. Very Large Scale Integr. Syst., 1995
IEEE Des. Test Comput., 1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Proceedings of the 1995 International Conference on Computer Design (ICCD '95), 1995
1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Proceedings of the 30th Design Automation Conference. Dallas, 1993
Performance Specification and Measurement.
Proceedings of the Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications, 1993
1992
Proceedings of the conference on European design automation, 1992
Proceedings of the 29th Design Automation Conference, 1992
1991
Proceedings of the First Great Lakes Symposium on VLSI, 1991
Proceedings of the Computer Aided Verification, 3rd International Workshop, 1991
1990
On the notion of the normal form register-level structures and its applications in design-space exploration.
Proceedings of the European Design Automation Conference, 1990
1986
Proceedings of the 19th annual workshop on Microprogramming, 1986
1978
Proceedings of the IEEE Computer Society's Second International Computer Software and Applications Conference, 1978