Grace Zgheib

According to our database1, Grace Zgheib authored at least 20 papers between 2011 and 2022.

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Bibliography

2022
Detailed Placement for Dedicated LUT-Level FPGA Interconnect.
ACM Trans. Reconfigurable Technol. Syst., 2022

2021
Clock Skew Scheduling: Avoiding the Runtime Cost of Mixed-Integer Linear Programming.
Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

2020
Timing-Driven Placement for FPGA Architectures with Dedicated Routing Paths.
Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Straight to the Point: Intra- and Intercluster LUT Connections to Mitigate the Delay of Programmable Routing.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

Architectural Enhancements in Intel® Agilex™ FPGAs.
Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019
Finding a Needle in the Haystack of Hardened Interconnect Patterns.
Proceedings of the 29th International Conference on Field Programmable Logic and Applications, 2019

2017
Leading the Blind - Automated Transistor-Level Modeling for FPGA Architects.
PhD thesis, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.
Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Evaluating FPGA clusters under wide ranges of design parameters.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

NAND-NOR: A Compact, Fast, and Delay Balanced FPGA Logic Element.
Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

2016
Automatic wire modeling to explore novel FPGA architectures.
Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

FPRESSO: Enabling Express Transistor-Level Exploration of FPGA Architectures.
Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

2015
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations.
J. Circuits Syst. Comput., 2015

An Ant Colony Optimization Heuristic to Optimize Prediction of Stability of Object-Oriented Components.
Proceedings of the 2015 IEEE International Conference on Information Reuse and Integration, 2015

Improved carry chain mapping for the VTR flow.
Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

A technology mapper for depth-constrained FPGA logic cells.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

2014
Revisiting and-inverter cones.
Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

2013
Shadow And-Inverter Cones.
Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Shadow AICs: reaping the benefits of and-inverter cones with minimal architectural impact (abstract only).
Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

2011
Reducing the pressure on routing resources of FPGAs with generic logic chains.
Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011


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