J. Kelly Flanagan

According to our database1, J. Kelly Flanagan authored at least 23 papers between 1987 and 2005.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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Links

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Bibliography

2005
A Trace-Driven Simulator For Palm OS Devices.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

2002
Simulating L3 Caches in Real Time Using Hardware Accelerated Cache Simulation (HACS): A Case Study with SPECint 2000.
Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 2002

2001
A national trace collection and distribution resource.
SIGARCH Comput. Archit. News, 2001

2000
Facilitating level three cache studies using set sampling.
Proceedings of the 32nd conference on Winter simulation, 2000

A first year computer organization course on the web: make the magic disappear.
Proceedings of the 2000 workshop on Computer architecture education, 2000

1999
Performance Surface Prediction for WAN-Based Clusters.
J. Supercomput., 1999

A System-Assisted Disk I/O Simulation Technique.
Proceedings of the MASCOTS 1999, 1999

1998
Low-power memory hierarchies: an argument for second-level caches.
Microprocess. Microsystems, 1998

Performance Surface Prediction for WAN-Based Clusters.
Proceedings of the Thirty-First Annual Hawaii International Conference on System Sciences, 1998

1997
A Stochastic Disk I/O Simulation Technique.
Proceedings of the 29th conference on Winter simulation, 1997

The Chordal Spoke ATM Interconnection Network.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1997

1996
Constructing instruction traces from cache-filtered address traces (CITCAT).
SIGARCH Comput. Archit. News, 1996

Cost Optimal Analysis for Workstation Clusters.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1996

Transaction Processing Workloads - A Comparison to the SPEC Benchmarks Using Memory Hierarchy Performance Studies.
Proceedings of the MASCOTS '96, 1996

The Inaccuracy of Trace-Driven Simulation Using Incomplete Mulitprogramming Trace Data.
Proceedings of the MASCOTS '96, 1996

1995
The Round Table ATM Interconnection Network.
Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 1995

1993
BACH: a hardware monitor for tracing microprocessor-based systems.
Microprocess. Microsystems, 1993

Incomplete Trace Data and Trace Driven Simulation.
Proceedings of the MASCOTS '93, 1993

1991
Performance analysis of inclusion effects in multi-level multiprocessor caches.
Proceedings of the Third IEEE Symposium on Parallel and Distributed Processing, 1991

1989
A method for computing the DFT of vector quantized data.
Proceedings of the IEEE International Conference on Acoustics, 1989

Vector quantization codebook generation using simulated annealing.
Proceedings of the IEEE International Conference on Acoustics, 1989

1988
Processor design using path programmable logic.
Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

1987
A multiprogrammed parallel architecture for digital signal processing.
Proceedings of the IEEE International Conference on Acoustics, 1987


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