J. Robert Jump

According to our database1, J. Robert Jump authored at least 35 papers between 1969 and 1994.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Awards

IEEE Fellow

IEEE Fellow 1995, "For contributions to the theory and design of interconnection networks for parallel computer systems.".

Timeline

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Links

On csauthors.net:

Bibliography

1994
Execution-Driven Simulation of Multiprocessors: Address and Timing Analysis.
ACM Trans. Model. Comput. Simul., 1994

Execution-Driven Simulation of a Superscalar Processor.
Proceedings of the 27th Annual Hawaii International Conference on System Sciences (HICSS-27), 1994

1993
NETSIM: A General-Purpose Interconnection Network Simulator.
Proceedings of the MASCOTS '93, 1993

Execution-Driven Simulation of Shared-Memory Multiprocessors.
Proceedings of the MASCOTS '93, 1993

1991
Efficient Simulation of Parallel Computer Systems.
Int. J. Comput. Simul., 1991

1990
Evaluation of Reduced Bandwidth Multistage Networks.
J. Parallel Distributed Comput., 1990

Efficient Simulation of Multiprogramming.
Proceedings of the 1990 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1990

1989
Efficient simulation of cache memories.
Proceedings of the 21st Winter Simulation Conference, 1989

Cross-profiling as an efficient technique in simulating parallel computer systems.
Proceedings of the 13th Annual International Computer Software and Applications Conference, 1989

1988
The Rice Parallel Processing Testbed.
Proceedings of the 1988 ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1988

1987
Vector Access Performance in Parallel Memories Using a Skewed Storage Scheme.
IEEE Trans. Computers, 1987

Performance Evaluation of Reduced Bandwidth Multistage Interconnection Networks.
Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987

1986
Performance of Unbuffered Shuffle-Exchange Networks.
IEEE Trans. Computers, 1986

Performance Evaluation of Vector Accesses in Parallel Memories Using a Skewed Storage Scheme.
Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

1985
Switching Strategies in Shuffle-Exchange Packet-Switched Networks.
IEEE Trans. Computers, 1985

Matrix Multiplication in an Interleaved Array Processing Architecture.
Proceedings of the 12th Annual Symposium on Computer Architecture, 1985

1984
Performance enhancement in buffered delta networks using crossbar switches and multiple links.
J. Parallel Distributed Comput., 1984

An interleaved array-processing architecture.
Proceedings of the American Federation of Information Processing Societies: 1984 National Computer Conference, 1984

1983
Switching Strategies in a Class of Packet Switching Networks
Proceedings of the 10th Annual Symposium on Computer Architecture, 1983, 1983

Generalized Delta Networks.
Proceedings of the International Conference on Parallel Processing, 1983

1982
Augmented and pruned n log n multistaged networks: topology and performance.
Proceedings of the International Conference on Parallel Processing, 1982

1981
Analysis and Simulation of Buffered Delta Networks.
IEEE Trans. Computers, 1981

Packet Switching Interconnection Networks for Modular Systems.
Computer, 1981

1979
On Functional Equivalences in a Model for Parallel Computation
Inf. Control., June, 1979

Top-Down Design in the Context of Parallel Programs
Inf. Control., March, 1979

1978
Effective Pipelining of Digital Systems.
IEEE Trans. Computers, 1978

1977
A Modular Memory Scheme for Array Processing.
Proceedings of the 4th Annual Symposium on Computer Architecture, 1977

1975
On the Interconnection of Asynchronous Control Structures.
J. ACM, 1975

1974
On the Interconnection Structure of Cellular Networks
Inf. Control., January, 1974

Asynchronous Control Arrays.
IEEE Trans. Computers, 1974

1973
On the Equivalence of Asynchronous Control Structures.
SIAM J. Comput., 1973

1972
Microprogrammed Arrays.
IEEE Trans. Computers, 1972

1971
On the Length of Feedback Shift Registers
Inf. Control., November, 1971

1970
R70-29 Uniform Synthesis of Sequential Circuits.
IEEE Trans. Computers, 1970

1969
A Note on the Iterative Decomposition of Finite Automata
Inf. Control., November, 1969


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