Sandhya Dwarkadas

According to our database1, Sandhya Dwarkadas authored at least 110 papers between 1989 and 2022.

Collaborative distances:

Awards

ACM Fellow

ACM Fellow 2018, "For contributions to shared memory and reconfigurability".

IEEE Fellow

IEEE Fellow 2017, "For contributions to shared memory and reconfigurability".

Timeline

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In proceedings 
Article 
PhD thesis 
Other 

Links

On csauthors.net:

Bibliography

2022
MAPPER: Managing Application Performance via Parallel Efficiency Regulation*.
ACM Trans. Archit. Code Optim., 2022

2021
TimeCache: Using Time to Eliminate Cache Side Channels when Sharing Software.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Performance Characterization of HTAP Workloads.
Proceedings of the 37th IEEE International Conference on Data Engineering, 2021

Interference-aware Micro-architectural Resource Manager for Hybrid Workloads.
Proceedings of the 11th Conference on Innovative Data Systems Research, 2021

2020
Timing Cache Accesses to Eliminate Side Channels in Shared Software.
CoRR, 2020

2019
Top Picks in Computer Architecture from Conferences in 2018.
IEEE Micro, 2019

Managing application parallelism via parallel efficiency regulation: poster.
Proceedings of the 24th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2019

On the Impact of Instruction Address Translation Overhead.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2019

2018
2018 Maurice Wilkes Award Given to Gabriel Loh.
IEEE Micro, 2018

Shielding Software From Privileged Side-Channel Attacks.
Proceedings of the 27th USENIX Security Symposium, 2018

Spectres, virtual ghosts, and hardware support.
Proceedings of the 7th International Workshop on Hardware and Architectural Support for Security and Privacy, 2018

2016
Introduction to the Special Issue on PPoPP'14.
ACM Trans. Parallel Comput., 2016

Coherence Stalls or Latency Tolerance: Informed CPU Scheduling for Socket and Core Sharing.
Proceedings of the 2016 USENIX Annual Technical Conference, 2016

Shared address translation revisited.
Proceedings of the Eleventh European Conference on Computer Systems, 2016

2015
Data Sharing or Resource Contention: Toward Performance Transparency on Multicore Systems.
Proceedings of the 2015 USENIX Annual Technical Conference, 2015

Characterization of Shared Library Access Patterns of Android Applications.
Proceedings of the 2015 IEEE International Symposium on Workload Characterization, 2015

2013
An Application-Tailored Approach to Hardware Cache Coherence.
Computer, 2013

Protozoa: adaptive granularity cache coherence.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

Verifying safety and liveness for the FlexTM hybrid transactional memory.
Proceedings of the Design, Automation and Test in Europe, 2013

Power containers: an OS facility for fine-grained power and energy management on multicore servers.
Proceedings of the Architectural Support for Programming Languages and Operating Systems, 2013

2012
Power and energy containers for multicore servers.
Proceedings of the ACM SIGMETRICS/PERFORMANCE Joint International Conference on Measurement and Modeling of Computer Systems, 2012

Amoeba-Cache: Adaptive Blocks for Eliminating Waste in the Memory Hierarchy.
Proceedings of the 45th Annual IEEE/ACM International Symposium on Microarchitecture, 2012

A Flexible Framework for Throttling-Enabled Multicore Management (TEMM).
Proceedings of the 41st International Conference on Parallel Processing, 2012

2011
Software Distributed Shared Memory.
Proceedings of the Encyclopedia of Parallel Computing, 2011

Analyzing Conflicts in Hardware-Supported Memory Transactions.
Int. J. Parallel Program., 2011

Hierarchical Parallelization of Gene Differential Association Analysis.
BMC Bioinform., 2011

SPATL: Honey, I Shrunk the Coherence Directory.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

POPS: Coherence Protocol Optimization for Both Private and Shared Data.
Proceedings of the 2011 International Conference on Parallel Architectures and Compilation Techniques, 2011

2010
Implementation tradeoffs in the design of flexible transactional memory support.
J. Parallel Distributed Comput., 2010

An Evaluation of Per-Chip Nonuniform Frequency Scaling on Multicores.
Proceedings of the 2010 USENIX Annual Technical Conference, 2010

Sentry: light-weight auxiliary memory access control.
Proceedings of the 37th International Symposium on Computer Architecture (ISCA 2010), 2010

SPACE: sharing pattern-based directory coherence for multicore scalability.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Tapping into Parallelism with Transactional Memory.
login Usenix Mag., 2009

Hardware Execution Throttling for Multi-core Resource Management.
Proceedings of the 2009 USENIX Annual Technical Conference, 2009

Refereeing conflicts in hardware transactional memory.
Proceedings of the 23rd international conference on Supercomputing, 2009

Towards practical page coloring-based multicore cache management.
Proceedings of the 2009 EuroSys Conference, Nuremberg, Germany, April 1-3, 2009, 2009

DDCache: Decoupled and Delegable Cache Data and Metadata.
Proceedings of the PACT 2009, 2009

2008
Flexible Decoupled Transactional Memory Support.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Hardware counter driven on-the-fly request signatures.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

Improving support for locality and fine-grain sharing in chip multiprocessors.
Proceedings of the 17th International Conference on Parallel Architectures and Compilation Techniques, 2008

2007
Nonblocking transactions without indirection using alert-on-update.
Proceedings of the SPAA 2007: Proceedings of the 19th Annual ACM Symposium on Parallelism in Algorithms and Architectures, 2007

Alert-on-update: a communication aid for shared memory multiprocessors.
Proceedings of the 12th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2007

An integrated hardware-software approach to flexible transactional memory.
Proceedings of the 34th International Symposium on Computer Architecture (ISCA 2007), 2007

Processor Hardware Counter Statistics as a First-Class System Resource.
Proceedings of HotOS'07: 11th Workshop on Hot Topics in Operating Systems, 2007

Analysis of input-dependent program behavior using active profiling.
Proceedings of the Workshop on Experimental Computer Science, 2007

2006
Compatible phase co-scheduling on a CMP of multi-threaded processors.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

Program phase detection and exploitation.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

2005
Shared memory computing on clusters with symmetric multiprocessors and system area networks.
ACM Trans. Comput. Syst., 2005

Low traffic overlay networks with large routing tables.
Proceedings of the International Conference on Measurements and Modeling of Computer Systems, 2005

Partitioning Multi-Threaded Processors with a Large Number of Threads.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2005

2004
Profile-Driven Component Placement for Cluster-Based Online Services.
IEEE Distributed Syst. Online, 2004

Parallel Metropolis coupled Markov chain Monte Carlo for Bayesian phylogenetic inference.
Bioinform., 2004

On scaling latent semantic indexing for large peer-to-peer systems.
Proceedings of the SIGIR 2004: Proceedings of the 27th Annual International ACM SIGIR Conference on Research and Development in Information Retrieval, 2004

Hybrid Global-Local Indexing for Efficient Peer-to-Peer Information Retrieval.
Proceedings of the 1st Symposium on Networked Systems Design and Implementation (NSDI 2004), 2004

Integrating Remote Invocation and Distributed Shared State.
Proceedings of the 18th International Parallel and Distributed Processing Symposium (IPDPS 2004), 2004

Hiding Synchronization Delays in a GALS Processor Microarchitecture.
Proceedings of the 10th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2004), 2004

2003
A Dynamically Tunable Memory Hierarchy.
IEEE Trans. Computers, 2003

Dynamic Frequency and Voltage Scaling for a Multiple-Clock-Domain Microprocessor.
IEEE Micro, 2003

Dynamically Tuning Processor Resources with Adaptive Processing.
Computer, 2003

Garbage Collector Assisted Memory Offloading for Memory-Constrained Devices.
Proceedings of the 5th IEEE Workshop on Mobile Computing Systems and Applications (WMCSA 2003), 2003

Peer-to-peer information retrieval using self-organizing semantic overlay networks.
Proceedings of the ACM SIGCOMM 2003 Conference on Applications, 2003

Exploiting high-level coherence information to optimize distributed shared state.
Proceedings of the ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, 2003

Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.
Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Dynamically Managing the Communication-Parallelism Trade-off in Future Clustered Processors.
Proceedings of the 30th International Symposium on Computer Architecture (ISCA 2003), 2003

Efficient Distributed Shared State for Heterogeneous Machine Architectures.
Proceedings of the 23rd International Conference on Distributed Computing Systems (ICDCS 2003), 2003

Distributed Shared State.
Proceedings of the 9th IEEE International Workshop on Future Trends of Distributed Computing Systems (FTDCS 2003), 2003

Characterizing and Predicting Program Behavior and its Variability.
Proceedings of the 12th International Conference on Parallel Architectures and Compilation Techniques (PACT 2003), 27 September, 2003

2002
Shared State for Distributed Interactive Data Mining Applications.
Distributed Parallel Databases, 2002

Early-Stage Definition of LPX: A Low Power Issue-Execute Processor.
Proceedings of the Power-Aware Computer Systems, Second International Workshop, 2002

Dynamic frequency and voltage control for a multiple clock domain microarchitecture.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

Managing static leakage energy in microprocessor functional units.
Proceedings of the 35th Annual International Symposium on Microarchitecture, 2002

A Technique for Adaptation to Available Resources on Clusters Independent of Synchronization Methods Used.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

Multi-Level Shared State for Distributed Systems.
Proceedings of the 31st International Conference on Parallel Processing (ICPP 2002), 2002

Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling.
Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), 2002

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power.
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques (PACT 2002), 2002

2001
Shared State for Client-Server Mining.
Proceedings of the First SIAM International Conference on Data Mining, 2001

Dynamic adaptation to available resources for parallel computing in an autonomous network of workstations.
Proceedings of the 2001 ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPOPP'01), 2001

Reducing the complexity of the register file in dynamic superscalar processors.
Proceedings of the 34th Annual International Symposium on Microarchitecture, 2001

Dynamically allocating processor resources between nearby and distant ILP.
Proceedings of the 28th Annual International Symposium on Computer Architecture, 2001

2000
Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures.
Proceedings of the 33rd Annual IEEE/ACM International Symposium on Microarchitecture, 2000

InterWeave: A Middleware System for Distributed Shared State.
Proceedings of the Languages, 2000

The Effect of Network Total Order, Broadcast, and Remote-Write Capability on Network-Based Shared Memory Computing.
Proceedings of the Sixth International Symposium on High-Performance Computer Architecture, 2000

1999
CRAUL: Compiler and run-time integration for adaptation under load.
Sci. Program., 1999

Combining compile-time and run-time support for efficient software distributed shared memory.
Proc. IEEE, 1999

Adaptive protocols for software distributed shared memory.
Proc. IEEE, 1999

Active Mining in a Distributed Setting.
Proceedings of the Large-Scale Parallel Data Mining, 1999

Cashmere-VLM: Remote Memory Paging for Software Distributed Shared Memory.
Proceedings of the 13th International Parallel Processing Symposium / 10th Symposium on Parallel and Distributed Processing (IPPS / SPDP '99), 1999

Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory.
Proceedings of the Fifth International Symposium on High-Performance Computer Architecture, 1999

Incremental and Interactive Sequence Mining.
Proceedings of the 1999 ACM CIKM International Conference on Information and Knowledge Management, 1999

1998
InterAct: Virtual Sharing for Interactive Client-Server Applications.
Proceedings of the Languages, 1998

Compiler and Run-Time Support for Adaptive Load Balancing in Software Distributed Shared Memory Systems.
Proceedings of the Languages, 1998

1997
Quantifying the Performance Differences between PVM and TreadMarks.
J. Parallel Distributed Comput., 1997

Cashmere-2L: Software Coherent Shared Memory on a Clustered Remote-Write Network.
Proceedings of the Sixteenth ACM Symposium on Operating System Principles, 1997

Compiler and Software Distributed Shared Memory Support for Irregular Applications.
Proceedings of the Sixth ACM SIGPLAN Symposium on Principles & Practice of Parallel Programming (PPOPP), 1997

VM-Based Shared Memory on Low-Latency, Remote-Memory-Access Networks.
Proceedings of the 24th International Symposium on Computer Architecture, 1997

Evaluating the Performance of Software Distributed Shared Memory as a Target for Parallelizing Compilers.
Proceedings of the 11th International Parallel Processing Symposium (IPPS '97), 1997

Software DSM Protocols that Adapt between Single Writer and Multiple Writer.
Proceedings of the 3rd IEEE Symposium on High-Performance Computer Architecture (HPCA '97), 1997

1996
ThreadMarks: Shared Memory Computing on Networks of Workstations.
Computer, 1996

A Comparison of Entry Consistency and Lazy Release Consistency Implementations.
Proceedings of the Second International Symposium on High-Performance Computer Architecture, 1996

An Integrated Compile-Time/Run-Time Software Distributed Shared Memory System.
Proceedings of the ASPLOS-VII Proceedings, 1996

1995
An Evaluation of Software-Based Release Consistent Protocols.
J. Parallel Distributed Comput., 1995

Message Passing Versus Distributed Shared Memory on Networks of Workstations.
Proceedings of the Proceedings Supercomputing '95, San Diego, CA, USA, December 4-8, 1995, 1995

1994
Execution-Driven Simulation of Multiprocessors: Address and Timing Analysis.
ACM Trans. Model. Comput. Simul., 1994

TreadMarks: Distributed Shared Memory on Standard Workstations and Operating Systems.
Proceedings of the USENIX Winter 1994 Technical Conference, 1994

Software Versus Hardware Shared-Memory Implementation: A Case Study.
Proceedings of the 21st Annual International Symposium on Computer Architecture. Chicago, 1994

1993
Execution-Driven Simulation of Shared-Memory Multiprocessors.
Proceedings of the MASCOTS '93, 1993

Evaluation of Release Consistent Software Distributed Shared Memory on Emerging Network Technology.
Proceedings of the 20th Annual International Symposium on Computer Architecture, 1993

1992
Willow: A Scalable Shared Memory Multiprocessor.
Proceedings of the Proceedings Supercomputing '92, 1992

1991
Efficient Simulation of Parallel Computer Systems.
Int. J. Comput. Simul., 1991

1989
Efficient simulation of cache memories.
Proceedings of the 21st Winter Simulation Conference, 1989


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