J. V. R. Ravindra
Affiliations:- Vardhaman College of Engineering, Shamshabad, Kacharam, Hyderabad, Telangana, India
According to our database1,
J. V. R. Ravindra
authored at least 22 papers
between 2005 and 2023.
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Bibliography
2023
Correction to: Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.
Wirel. Pers. Commun., 2023
Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.
Wirel. Pers. Commun., 2023
2022
Sustain. Comput. Informatics Syst., 2022
2021
Accuracy evaluation of a trained neural network by energy efficient approximate 4: 2 compressor.
Comput. Electr. Eng., 2021
2020
The enhancement of security measures in advanced encryption standard using double precision floating point multiplication model.
Trans. Emerg. Telecommun. Technol., 2020
2019
Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise Multipliers.
Proceedings of the 32nd International Conference on VLSI Design and 18th International Conference on Embedded Systems, 2019
Low-Power. High-Speed Adversarial Attack based 4: 2 Compressor as Full Adder for Multipliers in FIR Digital Filters.
Proceedings of the 2019 IEEE Nordic Circuits and Systems Conference, 2019
2018
Proceedings of the International SoC Design Conference, 2018
Performance Metrics of Imprecise Multipliers Based on Proximate Compressors for IIR Filters.
Proceedings of the 30th International Conference on Microelectronics, 2018
2016
Power and area calibration of switch arbiter for high speed switch control and scheduling in network-on-chip.
Proceedings of the International SoC Design Conference, 2016
Proceedings of the 2016 International Conference on Advances in Computing, 2016
2013
A Novel Analytical Model for Analysis of Delay and Crosstalk in Non Linear RLC Interconnects for Ultra Low Power Applications.
Proceedings of the 15th International Conference on Computer Modelling and Simulation, 2013
Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013
Power Aware and Delay Efficient Hybrid CMOS Full-Adder for Ultra Deep Submicron Technology.
Proceedings of the Seventh UKSim/AMSS European Modelling Symposium, 2013
2008
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
J. Circuits Syst. Comput., 2007
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
2005
A novel deep submicron low power bus coding technique.
Proceedings of the Third IASTED International Conference on Circuits, 2005