M. B. Srinivas

According to our database1, M. B. Srinivas authored at least 118 papers between 2003 and 2020.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2020
A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles.
IEEE Trans. Ind. Informatics, 2020

Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
An Improved Logarithmic Multiplier for Media Processing.
J. Signal Process. Syst., 2019

A frequency domain beamspace adaptive receive beamformer for ultrasound imaging systems: phantom simulation results.
Signal Image Video Process., 2019

Levin's Transformation-based Continuous-Time Linear-Phase Selective Filters.
Circuits Syst. Signal Process., 2019

2018
Synthesis of Ternary Logic Circuits Using 2: 1 Multiplexers.
IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Energy efficient design of CNFET-based multi-digit ternary adders.
Microelectron. J., 2018

A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application.
IEEE J. Solid State Circuits, 2018

Improved designs of digit-by-digit decimal multiplier.
Integr., 2018

Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter Approximation.
Circuits Syst. Signal Process., 2018

An Ultra Low Power, 10-Bit Two-Step Flash ADC for Signal Processing Applications.
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018

Design Methodologies for Ternary Logic Circuits.
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018

2017
A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

A low power, programmable bias inverter quantizer (BIQ) flash ADC.
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017

T2A: Analog and RF circuits.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

An ESOP Based Cube Decomposition Technique for Reversible Circuits.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Optimizing the Reversible Circuits Using Complementary Control Line Transformation.
Proceedings of the Reversible Computation - 9th International Conference, 2017

Ultra Low Power Programmable Wireless ExG SoC Design for IoT Healthcare System.
Proceedings of the Wireless Mobile Communication and Healthcare, 2017

A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017

2016
A Soft Computing Approach for Data Routing in Hospital Area Networks (HAN).
Int. J. Bus. Data Commun. Netw., 2016

A Hybrid Energy Efficient Digital Comparator.
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016

An Efficient Design Methodology for CNFET Based Ternary Logic Circuits.
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016

Modeling of EXG (ECG, EMG and EEG) non-idealities using MATLAB.
Proceedings of the 9th International Congress on Image and Signal Processing, 2016

An Iterative Logarithmic Multiplier with Improved Precision.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016

2014
A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal Converter.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

An Optimized Design of Reversible Quantum Comparator.
Proceedings of the 2014 27th International Conference on VLSI Design and 2014 13th International Conference on Embedded Systems, 2014

A reconfigurable 0-L1-L2 S-MASH<sup>2</sup> modulator with high-level sizing and power estimation.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014

A New Design of an N-Bit Reversible Arithmetic Logic Unit.
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014

Estimation of Arterial Stiffness through Pulse Transit Time Measurement.
Proceedings of the BIODEVICES 2014, 2014

A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014

2013
A smart phone/tablet based mobile health care system for developing countries.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

Uniform approximation of Gaussian wavelet for biomedical signal processing in analog domain.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

2012
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
Proceedings of the 25th International Conference on VLSI Design, 2012

Design of Prefix-Based Optimal Reversible Comparator.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

Design and Analysis of Reversible Ripple, Prefix and Prefix-Ripple Hybrid Adders.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012

A Modified Twin Precision Multiplier with 2D Bypassing Technique.
Proceedings of the International Symposium on Electronic System Design, 2012

CNFET based ternary magnitude comparator.
Proceedings of the International Symposium on Communications and Information Technologies, 2012

On the Suitability of Multi-Core Processing for Embedded Automotive Systems.
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012

2011
A Prefix Based Reconfigurable Adder.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
Proceedings of the International Symposium on Electronic System Design, 2011

A Multiple-Bandwidth 10-bit SAR Analog to Digital Converter.
Proceedings of the International Symposium on Electronic System Design, 2011

Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011

A Unified Architecture for BCD and Binary Adder/Subtractor.
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011

2010
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
J. Low Power Electron., 2010

An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010

A Novel, Variable Resolution Flash ADC with Sub Flash Architecture.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010

Effects of channel SNR in mobile cognitive radios and coexisting deployment of cognitive wireless sensor networks.
Proceedings of the 29th International Performance Computing and Communications Conference, 2010

A new approach to minimize leakage power in nano-scale VLSI adder.
Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010

A low power, variable resolution two-step flash ADC.
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

Implementation of low power FFT structure using a method based on conditionally coded blocks.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

An efficient ODT calibration scheme for improved signal integrity in memory interface.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

2009
Efficient Reversible Logic Design of BCD Subtractors.
Trans. Comput. Sci., 2009

A Novel Low Power, Variable Resolution Flash Analog-to-Digital Converter.
J. Low Power Electron., 2009

Design of a Low Power, Variable-Resolution Flash ADC.
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009

A novel low power, variable resolution pipelined ADC.
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009

Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks.
Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, 2009

A High Performance Unified BCD and Binary Adder/Subtractor.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

All Digital Duty Cycle Correction Circuit in 90nm Based on Mutex.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009

2008
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008

Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks.
Proceedings of the IEEE International Conference on Sensor Networks, 2008

A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008

Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008

Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008

2007
New and Improved Architectures for Montgomery Modular Multiplication.
Mob. Networks Appl., 2007

Delay and Energy Efficient Coding Techniques for Capacitive Interconnects.
J. Circuits Syst. Comput., 2007

Novel Architectures for High-Speed and Low-Power 3-2, 4-2 and 5-2 Compressors.
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n).
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.
Proceedings of the IFIP VLSI-SoC 2007, 2007

Bus encoding schemes for minimizing delay in VLSI interconnects.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007

A Comparative Study of Different FFT Architectures for Software Defined Radio.
Proceedings of the Embedded Computer Systems: Architectures, 2007

Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007

Novel, High-Speed 16-Digit BCD Adders Conforming to IEEE 754r Format.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007

Novel High-Speed Redundant Binary to Binary converter using Prefix Networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Novel architectures for efficient (m, n) parallel counters.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Area Efficient High Speed Architecture of Bruun's FFT for Software Defined Radio.
Proceedings of the Global Communications Conference, 2007

Rule Selection in Fuzzy Systems using Heuristics and Branch Prediction.
Proceedings of the IEEE Symposium on Foundations of Computational Intelligence, 2007

A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Reduced Area Low Power High Throughput BCD Adders for IEEE 754r Format
CoRR, 2006

VLSI Implementation of RSA Encryption System Using Ancient Indian Vedic Mathematics
CoRR, 2006

Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU
CoRR, 2006

An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates
CoRR, 2006

A New Reversible TSG Gate and Its Application For Designing Efficient Adder Circuits
CoRR, 2006

Novel BCD Adders and Their Reversible Logic Implementation for IEEE 754r Format.
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006

High-Throughput Montgomery Modular Multiplication.
Proceedings of the IFIP VLSI-SoC 2006, 2006

A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

An Efficient Reconfigurable Montgomery Multiplier Architecture for GF(n).
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

Modified Montgomery Modular Multiplication Using 4: 2 Compressor and CSA Adder.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006

A Generic Architecture for Intelligent System Hardware.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006

Novel Reversible Multiplier Architecture Using Reversible TSG Gate.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

Low Power Hierarchical Multiplier and Carry Look-Ahead Architecture.
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006

The New BCD Subtractor and Its Reversible Logic Implementation.
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005
Local Language Support for Handheld Devices.
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005

A 32-Bit Binary Floating Point Neuro-Chip.
Proceedings of the Advances in Natural Computation, First International Conference, 2005

A novel deep submicron low power bus coding technique.
Proceedings of the Third IASTED International Conference on Circuits, 2005

Implementation of A Fast Square In RSA Encryption/Decryption Architecture.
Proceedings of The 2005 International Conference on Security and Management, 2005

Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.
Proceedings of The 2005 International Conference on Security and Management, 2005

Reversible Logic Synthesis of Half, Full and Parallel Subtractors.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005

VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.
Proceedings of The 2005 International Conference on Scientific Computing, 2005

Verilog Coding Style for Efficient Synthesis In FPGA.
Proceedings of the 2005 International Conference on Computer Design, 2005

Design for A Fast And Low Power 2's Complement Multiplier.
Proceedings of the 2005 International Conference on Computer Design, 2005

Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.
Proceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, 2005

A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005

2003
Design of a digital CDMA receiver.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003

Speech encoding and encryption in VLSI.
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003


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