M. B. Srinivas
Orcid: 0000-0003-1555-3639Affiliations:
- BML Munjal University, Gurgaon, India
According to our database1,
M. B. Srinivas
authored at least 127 papers
between 2003 and 2023.
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Bibliography
2023
Hand gestures recognition using edge computing system based on vision transformer and lightweight CNN.
J. Ambient Intell. Humaniz. Comput., March, 2023
2022
IEEE Trans. Very Large Scale Integr. Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
SN Comput. Sci., 2022
Architecture slack exploitation for phase classification and performance estimation in server-class processors.
J. Parallel Distributed Comput., 2022
2021
'Glaucoma - Automating the Cup-to-Disc Ratio Estimation in Fundus Images by Combining Random Walk Algorithm with Otsu Thresholding'.
Proceedings of the 10th International IEEE/EMBS Conference on Neural Engineering, 2021
Proceedings of the 13th International Conference on COMmunication Systems & NETworkS, 2021
2020
A 7-Cell, Stackable, Li-Ion Monitoring and Active/Passive Balancing IC With In-Built Cell Balancing Switches for Electric and Hybrid Vehicles.
IEEE Trans. Ind. Informatics, 2020
Temperature Aware Adaptations for Improved Read Reliability in STT-MRAM Memory Subsystem.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
2019
J. Signal Process. Syst., 2019
A frequency domain beamspace adaptive receive beamformer for ultrasound imaging systems: phantom simulation results.
Signal Image Video Process., 2019
Circuits Syst. Signal Process., 2019
2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
Microelectron. J., 2018
A Digitally Calibrated Bandgap Reference With 0.06% Error for Low-Side Current Sensing Application.
IEEE J. Solid State Circuits, 2018
Nonlinear Sequence Transformation-Based Continuous-Time Wavelet Filter Approximation.
Circuits Syst. Signal Process., 2018
Proceedings of the 31st International Conference on VLSI Design and 17th International Conference on Embedded Systems, 2018
Proceedings of the 48th IEEE International Symposium on Multiple-Valued Logic, 2018
Proceedings of the IEEE International Symposium on Smart Electronic Systems, 2018
2017
A Switched-Capacitor Amplifier with True Rail-to-Rail Input Range without Using a Rail-to-Rail Op-Amp.
Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017
Proceedings of the 2017 IFIP/IEEE International Conference on Very Large Scale Integration, 2017
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
A low power, programmable 12-bit two step SAR-flash ADC for signal processing applications.
Proceedings of the 30th IEEE International System-on-Chip Conference, 2017
Proceedings of the Reversible Computation - 9th International Conference, 2017
Proceedings of the Reversible Computation - 9th International Conference, 2017
Proceedings of the Wireless Mobile Communication and Healthcare, 2017
A 0.32 µW, 76.8 dB SNDR Programmable Gain Instrumentation Amplifier for Bio-Potential Signal Processing Applications.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017
A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.
Proceedings of the 2017 39th Annual International Conference of the IEEE Engineering in Medicine and Biology Society (EMBC), 2017
2016
Int. J. Bus. Data Commun. Netw., 2016
Proceedings of the 29th International Conference on VLSI Design and 15th International Conference on Embedded Systems, 2016
Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2016
Proceedings of the 9th International Congress on Image and Signal Processing, 2016
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point Units.
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
Proceedings of the 2014 27th International Conference on VLSI Design, 2014
A reconfigurable 0-L1-L2 S-MASH<sup>2</sup> modulator with high-level sizing and power estimation.
Proceedings of the 27th IEEE International System-on-Chip Conference, 2014
Proceedings of the 2014 Fifth International Symposium on Electronic System Design, 2014
Proceedings of the BIODEVICES 2014, 2014
A unified flagged prefix constant addition-subtraction scheme for design of area and power efficient binary floating-point and constant integer arithmetic circuits.
Proceedings of the 2014 IEEE Asia Pacific Conference on Circuits and Systems, 2014
2013
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
Uniform approximation of Gaussian wavelet for biomedical signal processing in analog domain.
Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013
2012
Low-Power Self Reconfigurable Multiplexer Based Decoder for Adaptive Resolution Flash ADCs.
Proceedings of the 25th International Conference on VLSI Design, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2012
Proceedings of the International Symposium on Electronic System Design, 2012
Proceedings of the International Symposium on Communications and Information Technologies, 2012
Proceedings of the 2012 International Conference on Cyber-Enabled Distributed Computing and Knowledge Discovery, 2012
2011
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011
A Reconfigurable INC/DEC/2's Complement/Priority Encoder Circuit with Improved Decision Block.
Proceedings of the International Symposium on Electronic System Design, 2011
Proceedings of the International Symposium on Electronic System Design, 2011
Increment/decrement/2's complement/priority encoder circuit for varying operand lengths.
Proceedings of the 11th International Symposium on Communications and Information Technologies, 2011
Proceedings of the 14th Euromicro Conference on Digital System Design, 2011
2010
An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
J. Low Power Electron., 2010
An Alternative approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects.
Proceedings of the VLSI Design 2010: 23rd International Conference on VLSI Design, 2010
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Effects of channel SNR in mobile cognitive radios and coexisting deployment of cognitive wireless sensor networks.
Proceedings of the 29th International Performance Computing and Communications Conference, 2010
Proceedings of the ICWET '10 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 26, 2010
Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010
Implementation of low power FFT structure using a method based on conditionally coded blocks.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
An efficient ODT calibration scheme for improved signal integrity in memory interface.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
Low power, variable resolution pipelined analog to Digital converter with sub flash architecture.
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010
2009
J. Low Power Electron., 2009
Proceedings of the VLSI Design 2009: Improving Productivity through Higher Abstraction, 2009
Proceedings of the Annual IEEE International SoC Conference, SoCC 2009, 2009
Multi-hop scheduling and local data link aggregation dependant Qos in modeling and simulation of power-aware wireless sensor networks.
Proceedings of the International Conference on Wireless Communications and Mobile Computing: Connecting the World Wirelessly, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
Transition Inversion Based Low Power Data Coding Scheme for Synchronous Serial Communication.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2009
2008
Proceedings of the 21st International Conference on VLSI Design (VLSI Design 2008), 2008
Training Data Compression Algorithms and Reliability in Large Wireless Sensor Networks.
Proceedings of the IEEE International Conference on Sensor Networks, 2008
A Novel Encoding Scheme for Delay and Energy Minimization in VLSI Interconnects with Built-In Error Detection.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2008
Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.
Proceedings of the 9th International Symposium on Quality of Electronic Design (ISQED 2008), 2008
Generic sub-space algorithm for generating reduced order models of linear time varying vlsi circuits.
Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, 2008
2007
Mob. Networks Appl., 2007
J. Circuits Syst. Comput., 2007
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A Unified, Reconfigurable Architecture for Montgomery Multiplication in Finite Fields GF(p) and GF(2^n).
Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007
A bit-sliced, scalable and unified montgomery multiplier architecture for RSA and ECC.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
A unified and reconfigurable Montgomery Multiplier architecture without four-to-two CSA.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Modeling and analysis of crosstalk for distributed RLC interconnects using difference model approach.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the Embedded Computer Systems: Architectures, 2007
Generating reduced order models using subspace iteration for linear RLC circuits in nanometer designs.
Proceedings of the 2nd Internationa ICST Conference on Nano-Networks, 2007
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN).
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007
Proceedings of the Global Communications Conference, 2007
Proceedings of the IEEE Symposium on Foundations of Computational Intelligence, 2007
A Statistical Model for Estimating the Effect of Process Variations on Delay and Slew Metrics for VLSI Interconnects.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007
2006
CoRR, 2006
Novel Reversible TSG Gate and Its Application for Designing Components of Primitive Reversible/Quantum ALU
CoRR, 2006
An Extension to DNA Based Fredkin Gate Circuits: Design of Reversible Sequential Circuits using Fredkin Gates
CoRR, 2006
CoRR, 2006
Proceedings of the 19th International Conference on VLSI Design (VLSI Design 2006), 2006
Proceedings of the IFIP VLSI-SoC 2006, 2006
A novel, coupling driven, low power bus coding technique for minimizing capacitive crosstalk in VLSI interconnects.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Minimizing Simultaneous Switching Noise (SSN) using Modified Odd/Even Bus Invert Method.
Proceedings of the Third IEEE International Workshop on Electronic Design, 2006
Novel and Efficient 4: 2 and 5: 2 Compressors with Minimum Number of Transistors Designed for Low-Power Operations.
Proceedings of the 2006 International Conference on Embedded Systems & Applications, 2006
Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems 2006, 2006
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006
Proceedings of the 2006 IEEE/ACS International Conference on Computer Systems and Applications (AICCSA 2006), 2006
Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006
2005
Proceedings of the International Symposium on Information Technology: Coding and Computing (ITCC 2005), 2005
Proceedings of the Advances in Natural Computation, First International Conference, 2005
A novel deep submicron low power bus coding technique.
Proceedings of the Third IASTED International Conference on Circuits, 2005
Implementation of A Fast Square In RSA Encryption/Decryption Architecture.
Proceedings of The 2005 International Conference on Security and Management, 2005
Faster RSA Encryption/Decryption Architecture Using an Efficient High Speed Overlay Multiplier.
Proceedings of The 2005 International Conference on Security and Management, 2005
Reversible Logic Synthesis of Half, Full and Parallel Subtractors.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005
A Reversible Version of 4 x 4 Bit Array Multiplier With Minimum Gates and Garbage Outputs.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005
A Need of Quantum Computing: Reversible Logic Synthesis of Parallel Binary Adder-Subtractor.
Proceedings of The 2005 International Conference on Embedded Systems and Applications, 2005
VLSI Implementation of O(n*n) Sorting Algorithms And Their Hardware Comparison.
Proceedings of The 2005 International Conference on Scientific Computing, 2005
Verilog Coding Style for Efficient Synthesis In FPGA.
Proceedings of the 2005 International Conference on Computer Design, 2005
Design for A Fast And Low Power 2's Complement Multiplier.
Proceedings of the 2005 International Conference on Computer Design, 2005
Design And Analysis of A VLSI Based High Performance Low Power Parallel Square Architecture.
Proceedings of the 2005 International Conference on Algorithmic Mathematics and Computer Science, 2005
A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.
Proceedings of the Advances in Computer Systems Architecture, 10th Asia-Pacific Conference, 2005
2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003
Proceedings of the 2003 Asia and South Pacific Design Automation Conference, 2003