P. Ramakrishna
This page is a disambiguation page, it actually contains multiple papers from persons of the same or a similar name.
Bibliography
2026
Design of an optimized parallel hardware architecture for efficient image haze removal.
Multim. Tools Appl., February, 2026
Optimized 2-D FIR filter bank architecture using various symmetries with parallel processing and DA.
Comput. Electr. Eng., 2026
2025
A 1.1-pJ/b/Lane, 1.8-Tb/s Chiplet Using 113-Gb/s PAM-4 Transceiver With Equalization Strategy to Reduce Fractionally Spaced 0.5-UI ISI in 5-nm CMOS.
IEEE Solid State Circuits Lett., 2025
Proceedings of the IEEE International Solid-State Circuits Conference, 2025
2024
A 1.1pJ/b/Lane, 1.8Tb/s Chiplet Over XSR-MCM Channels Using 113Gb/s PAM-4 Transceiver with Signal Equalization and Envelope Adaptation Using TX-FFE in 5nm CMOS.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
A 0.9pj/b 9.8-113Gb/s XSR SerDes with 6-tap TX FFE and AC coupling RX in 3nm FinFet Technology.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024
2023
Correction to: Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.
Wirel. Pers. Commun., 2023
Design and Implementation of Power-Efficient Cryptography Scheme Using a Novel Multiplication Technique.
Wirel. Pers. Commun., 2023
Proceedings of the 9th International Conference on Control, 2023
2022
Int. J. Speech Technol., 2022
A 1.6Tb/s Chiplet over XSR-MCM Channels using 113Gb/s PAM-4 Transceiver with Dynamic Receiver-Driven Adaptation of TX-FFE and Programmable Roaming Taps in 5nm CMOS.
Proceedings of the IEEE International Solid-State Circuits Conference, 2022